edcaf1a6a7
Make single kernel can be used on RBTX4927/37/38. Also make some SoC-specific code independent from board-specific code. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
170 lines
4.4 KiB
C
170 lines
4.4 KiB
C
/*
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* Toshiba RBTX4938 specific interrupt handlers
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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/*
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IRQ Device
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16 TX4938-CP0/00 Software 0
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17 TX4938-CP0/01 Software 1
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18 TX4938-CP0/02 Cascade TX4938-CP0
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19 TX4938-CP0/03 Multiplexed -- do not use
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20 TX4938-CP0/04 Multiplexed -- do not use
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21 TX4938-CP0/05 Multiplexed -- do not use
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22 TX4938-CP0/06 Multiplexed -- do not use
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23 TX4938-CP0/07 CPU TIMER
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24 TX4938-PIC/00
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25 TX4938-PIC/01
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26 TX4938-PIC/02 Cascade RBTX4938-IOC
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27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
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28 TX4938-PIC/04
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29 TX4938-PIC/05 TX4938 ETH1
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30 TX4938-PIC/06 TX4938 ETH0
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31 TX4938-PIC/07
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32 TX4938-PIC/08 TX4938 SIO 0
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33 TX4938-PIC/09 TX4938 SIO 1
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34 TX4938-PIC/10 TX4938 DMA0
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35 TX4938-PIC/11 TX4938 DMA1
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36 TX4938-PIC/12 TX4938 DMA2
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37 TX4938-PIC/13 TX4938 DMA3
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38 TX4938-PIC/14
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39 TX4938-PIC/15
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40 TX4938-PIC/16 TX4938 PCIC
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41 TX4938-PIC/17 TX4938 TMR0
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42 TX4938-PIC/18 TX4938 TMR1
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43 TX4938-PIC/19 TX4938 TMR2
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44 TX4938-PIC/20
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45 TX4938-PIC/21
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46 TX4938-PIC/22 TX4938 PCIERR
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47 TX4938-PIC/23
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48 TX4938-PIC/24
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49 TX4938-PIC/25
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50 TX4938-PIC/26
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51 TX4938-PIC/27
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52 TX4938-PIC/28
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53 TX4938-PIC/29
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54 TX4938-PIC/30
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55 TX4938-PIC/31 TX4938 SPI
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56 RBTX4938-IOC/00 PCI-D
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57 RBTX4938-IOC/01 PCI-C
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58 RBTX4938-IOC/02 PCI-B
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59 RBTX4938-IOC/03 PCI-A
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60 RBTX4938-IOC/04 RTC
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61 RBTX4938-IOC/05 ATA
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62 RBTX4938-IOC/06 MODEM
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63 RBTX4938-IOC/07 SWINT
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/mipsregs.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/rbtx4938.h>
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static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
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static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
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#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
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static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
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.name = TOSHIBA_RBTX4938_IOC_NAME,
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.ack = toshiba_rbtx4938_irq_ioc_disable,
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.mask = toshiba_rbtx4938_irq_ioc_disable,
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.mask_ack = toshiba_rbtx4938_irq_ioc_disable,
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.unmask = toshiba_rbtx4938_irq_ioc_enable,
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};
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static int toshiba_rbtx4938_irq_nested(int sw_irq)
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{
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u8 level3;
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level3 = readb(rbtx4938_imstat_addr);
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if (level3)
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/* must use fls so onboard ATA has priority */
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sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1;
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return sw_irq;
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}
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/**********************************************************************************/
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/* Functions for ioc */
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/**********************************************************************************/
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static void __init
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toshiba_rbtx4938_irq_ioc_init(void)
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{
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int i;
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for (i = RBTX4938_IRQ_IOC;
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i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
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set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
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handle_level_irq);
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set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
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}
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static void
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toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
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{
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unsigned char v;
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v = readb(rbtx4938_imask_addr);
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v |= (1 << (irq - RBTX4938_IRQ_IOC));
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writeb(v, rbtx4938_imask_addr);
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mmiowb();
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}
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static void
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toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
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{
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unsigned char v;
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v = readb(rbtx4938_imask_addr);
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v &= ~(1 << (irq - RBTX4938_IRQ_IOC));
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writeb(v, rbtx4938_imask_addr);
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mmiowb();
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}
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static int rbtx4938_irq_dispatch(int pending)
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{
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int irq;
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if (pending & STATUSF_IP7)
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irq = MIPS_CPU_IRQ_BASE + 7;
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else if (pending & STATUSF_IP2) {
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irq = txx9_irq();
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if (irq == RBTX4938_IRQ_IOCINT)
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irq = toshiba_rbtx4938_irq_nested(irq);
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} else if (pending & STATUSF_IP1)
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irq = MIPS_CPU_IRQ_BASE + 0;
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else if (pending & STATUSF_IP0)
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irq = MIPS_CPU_IRQ_BASE + 1;
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else
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irq = -1;
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return irq;
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}
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void __init rbtx4938_irq_setup(void)
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{
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txx9_irq_dispatch = rbtx4938_irq_dispatch;
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/* Now, interrupt control disabled, */
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/* all IRC interrupts are masked, */
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/* all IRC interrupt mode are Low Active. */
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/* mask all IOC interrupts */
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writeb(0, rbtx4938_imask_addr);
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/* clear SoftInt interrupts */
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writeb(0, rbtx4938_softint_addr);
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tx4938_irq_init();
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toshiba_rbtx4938_irq_ioc_init();
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/* Onboard 10M Ether: High Active */
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set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
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}
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