b04ec261bd
This patch fixes a bug of include/asm-m32r/system.h:__cmpxchg_u32(). static __inline__ unsigned long __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new); In __cmpxchg_u32(), the "old" value must not be changed to the previous "*p" value. But the former code modifies the previous "*p" value. A deadlock at _atomic_dec_and_lock sometimes happened due to this bug. Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
370 lines
11 KiB
C
370 lines
11 KiB
C
#ifndef _ASM_M32R_SYSTEM_H
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#define _ASM_M32R_SYSTEM_H
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 by Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
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* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#include <linux/config.h>
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#include <asm/assembler.h>
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#ifdef __KERNEL__
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'.
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*
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* `next' and `prev' should be struct task_struct, but it isn't always defined
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*/
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#ifndef CONFIG_SMP
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#define prepare_to_switch() do { } while(0)
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#endif /* not CONFIG_SMP */
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#define switch_to(prev, next, last) do { \
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register unsigned long arg0 __asm__ ("r0") = (unsigned long)prev; \
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register unsigned long arg1 __asm__ ("r1") = (unsigned long)next; \
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register unsigned long *oldsp __asm__ ("r2") = &(prev->thread.sp); \
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register unsigned long *newsp __asm__ ("r3") = &(next->thread.sp); \
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register unsigned long *oldlr __asm__ ("r4") = &(prev->thread.lr); \
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register unsigned long *newlr __asm__ ("r5") = &(next->thread.lr); \
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register struct task_struct *__last __asm__ ("r6"); \
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__asm__ __volatile__ ( \
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"st r8, @-r15 \n\t" \
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"st r9, @-r15 \n\t" \
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"st r10, @-r15 \n\t" \
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"st r11, @-r15 \n\t" \
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"st r12, @-r15 \n\t" \
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"st r13, @-r15 \n\t" \
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"st r14, @-r15 \n\t" \
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"seth r14, #high(1f) \n\t" \
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"or3 r14, r14, #low(1f) \n\t" \
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"st r14, @r4 ; store old LR \n\t" \
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"st r15, @r2 ; store old SP \n\t" \
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"ld r15, @r3 ; load new SP \n\t" \
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"st r0, @-r15 ; store 'prev' onto new stack \n\t" \
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"ld r14, @r5 ; load new LR \n\t" \
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"jmp r14 \n\t" \
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".fillinsn \n " \
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"1: \n\t" \
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"ld r6, @r15+ ; load 'prev' from new stack \n\t" \
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"ld r14, @r15+ \n\t" \
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"ld r13, @r15+ \n\t" \
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"ld r12, @r15+ \n\t" \
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"ld r11, @r15+ \n\t" \
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"ld r10, @r15+ \n\t" \
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"ld r9, @r15+ \n\t" \
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"ld r8, @r15+ \n\t" \
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: "=&r" (__last) \
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: "r" (arg0), "r" (arg1), "r" (oldsp), "r" (newsp), \
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"r" (oldlr), "r" (newlr) \
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: "memory" \
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); \
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last = __last; \
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} while(0)
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*
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* TODO: fill this in!
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*/
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static inline void sched_cacheflush(void)
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{
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}
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/* Interrupt Control */
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#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
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#define local_irq_enable() \
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__asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
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#define local_irq_disable() \
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__asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
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#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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static inline void local_irq_enable(void)
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{
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unsigned long tmpreg;
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__asm__ __volatile__(
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"mvfc %0, psw; \n\t"
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"or3 %0, %0, #0x0040; \n\t"
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"mvtc %0, psw; \n\t"
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: "=&r" (tmpreg) : : "cbit", "memory");
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}
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static inline void local_irq_disable(void)
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{
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unsigned long tmpreg0, tmpreg1;
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__asm__ __volatile__(
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"ld24 %0, #0 ; Use 32-bit insn. \n\t"
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"mvfc %1, psw ; No interrupt can be accepted here. \n\t"
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"mvtc %0, psw \n\t"
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"and3 %0, %1, #0xffbf \n\t"
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"mvtc %0, psw \n\t"
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: "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
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}
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#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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#define local_save_flags(x) \
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__asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
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#define local_irq_restore(x) \
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__asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
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: "r" (x) : "cbit", "memory")
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#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
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#define local_irq_save(x) \
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__asm__ __volatile__( \
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"mvfc %0, psw; \n\t" \
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"clrpsw #0x40 -> nop; \n\t" \
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: "=r" (x) : /* no input */ : "memory")
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#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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#define local_irq_save(x) \
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({ \
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unsigned long tmpreg; \
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__asm__ __volatile__( \
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"ld24 %1, #0 \n\t" \
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"mvfc %0, psw \n\t" \
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"mvtc %1, psw \n\t" \
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"and3 %1, %0, #0xffbf \n\t" \
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"mvtc %1, psw \n\t" \
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: "=r" (x), "=&r" (tmpreg) \
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: : "cbit", "memory"); \
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})
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#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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!(flags & 0x40); \
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})
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#define nop() __asm__ __volatile__ ("nop" : : )
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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#ifdef CONFIG_SMP
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extern void __xchg_called_with_bad_pointer(void);
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#endif
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#ifdef CONFIG_CHIP_M32700_TS1
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#define DCACHE_CLEAR(reg0, reg1, addr) \
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"seth "reg1", #high(dcache_dummy); \n\t" \
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"or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
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"lock "reg0", @"reg1"; \n\t" \
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"add3 "reg0", "addr", #0x1000; \n\t" \
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"ld "reg0", @"reg0"; \n\t" \
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"add3 "reg0", "addr", #0x2000; \n\t" \
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"ld "reg0", @"reg0"; \n\t" \
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"unlock "reg0", @"reg1"; \n\t"
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/* FIXME: This workaround code cannot handle kenrel modules
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* correctly under SMP environment.
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*/
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#else /* CONFIG_CHIP_M32700_TS1 */
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#define DCACHE_CLEAR(reg0, reg1, addr)
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#endif /* CONFIG_CHIP_M32700_TS1 */
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static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr,
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int size)
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{
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unsigned long flags;
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unsigned long tmp = 0;
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local_irq_save(flags);
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switch (size) {
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#ifndef CONFIG_SMP
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case 1:
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__asm__ __volatile__ (
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"ldb %0, @%2 \n\t"
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"stb %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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case 2:
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__asm__ __volatile__ (
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"ldh %0, @%2 \n\t"
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"sth %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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case 4:
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__asm__ __volatile__ (
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"ld %0, @%2 \n\t"
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"st %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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#else /* CONFIG_SMP */
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case 4:
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r4", "%2")
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"lock %0, @%2; \n\t"
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"unlock %1, @%2; \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r4"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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break;
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default:
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__xchg_called_with_bad_pointer();
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#endif /* CONFIG_SMP */
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}
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local_irq_restore(flags);
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return (tmp);
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}
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#define __HAVE_ARCH_CMPXCHG 1
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static __inline__ unsigned long
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__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
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{
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unsigned long flags;
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unsigned int retval;
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r4", "%1")
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M32R_LOCK" %0, @%1; \n"
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" bne %0, %2, 1f; \n"
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M32R_UNLOCK" %3, @%1; \n"
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" bra 2f; \n"
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" .fillinsn \n"
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"1:"
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M32R_UNLOCK" %0, @%1; \n"
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" .fillinsn \n"
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"2:"
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: "=&r" (retval)
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: "r" (p), "r" (old), "r" (new)
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: "cbit", "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r4"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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return retval;
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}
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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#if 0 /* we don't have __cmpxchg_u64 */
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case 8:
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return __cmpxchg_u64(ptr, old, new);
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#endif /* 0 */
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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#endif /* __KERNEL__ */
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/*
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* Memory barrier.
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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*/
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#define mb() barrier()
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#define rmb() mb()
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#define wmb() mb()
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/**
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like thiswhere there are no data dependencies.
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**/
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#define read_barrier_depends() do { } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while (0)
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#endif
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#define arch_align_stack(x) (x)
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#endif /* _ASM_M32R_SYSTEM_H */
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