a5a503038e
Patch from Vitaly Wool This patch adds kernel headers for PNX4008 ARM platform. It's basically the same as the previos one, but with the rmk's comments taken into account. Signed-off-by: Vitaly Wool <vwool@ru.mvista.com> Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
62 lines
2.1 KiB
C
62 lines
2.1 KiB
C
/*
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* include/asm-arm/arch-pnx4008/clock.h
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*
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* Clock control driver for PNX4008 - header file
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*
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* Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __PNX4008_CLOCK_H__
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#define __PNX4008_CLOCK_H__
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struct module;
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struct clk;
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#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
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#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40)
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#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44)
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#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48)
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#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c)
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#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50)
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#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58)
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#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64)
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#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68)
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#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80)
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#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84)
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#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90)
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#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac)
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#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0)
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#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4)
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#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8)
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#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4)
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#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8)
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#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0)
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#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4)
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#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8)
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#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec)
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#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc)
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#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
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#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60)
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#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64)
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#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68)
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#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C)
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#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
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#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE)
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#define CLK_RATE_13MHZ 13000
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#define CLK_RATE_1MHZ 1000
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#define CLK_RATE_208MHZ 208000
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#define CLK_RATE_48MHZ 48000
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#define CLK_RATE_32KHZ 32
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#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
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#endif
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