1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
412 lines
9.9 KiB
C
412 lines
9.9 KiB
C
/*
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* arch/ppc/platforms/lopec.c
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*
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* Setup routines for the Motorola LoPEC.
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*
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* Author: Dan Cox
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* Maintainer: Tom Rini <trini@kernel.crashing.org>
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/pci_ids.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <linux/seq_file.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/root_dev.h>
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#include <linux/pci.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/io.h>
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#include <asm/open_pic.h>
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#include <asm/i8259.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/mpc10x.h>
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#include <asm/hw_irq.h>
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#include <asm/prep_nvram.h>
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#include <asm/kgdb.h>
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/*
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* Define all of the IRQ senses and polarities. Taken from the
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* LoPEC Programmer's Reference Guide.
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*/
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static u_char lopec_openpic_initsenses[16] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 3 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 4 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 5 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 6 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 7 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 8 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 9 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 10 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 11 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ 12 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ 13 */
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(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ 14 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* IRQ 15 */
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};
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static inline int __init
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lopec_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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int irq;
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static char pci_irq_table[][4] = {
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{16, 0, 0, 0}, /* ID 11 - Winbond */
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{22, 0, 0, 0}, /* ID 12 - SCSI */
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{0, 0, 0, 0}, /* ID 13 - nothing */
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{17, 0, 0, 0}, /* ID 14 - 82559 Ethernet */
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{27, 0, 0, 0}, /* ID 15 - USB */
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{23, 0, 0, 0}, /* ID 16 - PMC slot 1 */
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{24, 0, 0, 0}, /* ID 17 - PMC slot 2 */
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{25, 0, 0, 0}, /* ID 18 - PCI slot */
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{0, 0, 0, 0}, /* ID 19 - nothing */
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{0, 0, 0, 0}, /* ID 20 - nothing */
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{0, 0, 0, 0}, /* ID 21 - nothing */
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{0, 0, 0, 0}, /* ID 22 - nothing */
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{0, 0, 0, 0}, /* ID 23 - nothing */
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{0, 0, 0, 0}, /* ID 24 - PMC slot 1b */
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{0, 0, 0, 0}, /* ID 25 - nothing */
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{0, 0, 0, 0} /* ID 26 - PMC Slot 2b */
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};
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const long min_idsel = 11, max_idsel = 26, irqs_per_slot = 4;
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irq = PCI_IRQ_TABLE_LOOKUP;
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if (!irq)
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return 0;
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return irq;
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}
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static void __init
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lopec_setup_winbond_83553(struct pci_controller *hose)
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{
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int devfn;
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devfn = PCI_DEVFN(11,0);
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/* IDE interrupt routing (primary 14, secondary 15) */
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early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
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/* PCI interrupt routing */
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early_write_config_word(hose, 0, devfn, 0x44, 0x0000);
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/* ISA-PCI address decoder */
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early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);
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/* RTC, kb, not used in PPC */
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early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
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early_write_config_byte(hose, 0, devfn, 0x4e, 0x04);
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devfn = PCI_DEVFN(11, 1);
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early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
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early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
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}
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static void __init
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lopec_find_bridges(void)
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{
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struct pci_controller *hose;
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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if (mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B,
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MPC10X_MAPB_EUMB_BASE) == 0) {
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hose->mem_resources[0].end = 0xffffffff;
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lopec_setup_winbond_83553(hose);
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = lopec_map_irq;
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}
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}
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static int
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lopec_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "machine\t\t: Motorola LoPEC\n");
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return 0;
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}
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static u32
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lopec_irq_canonicalize(u32 irq)
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{
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if (irq == 2)
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return 9;
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else
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return irq;
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}
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static void
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lopec_restart(char *cmd)
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{
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#define LOPEC_SYSSTAT1 0xffe00000
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/* force a hard reset, if possible */
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unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
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reg |= 0x80;
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*((unsigned char *) LOPEC_SYSSTAT1) = reg;
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local_irq_disable();
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while(1);
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#undef LOPEC_SYSSTAT1
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}
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static void
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lopec_halt(void)
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{
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local_irq_disable();
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while(1);
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}
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static void
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lopec_power_off(void)
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{
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lopec_halt();
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}
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#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
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int lopec_ide_ports_known = 0;
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static unsigned long lopec_ide_regbase[MAX_HWIFS];
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static unsigned long lopec_ide_ctl_regbase[MAX_HWIFS];
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static unsigned long lopec_idedma_regbase;
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static void
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lopec_ide_probe(void)
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{
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struct pci_dev *dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
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PCI_DEVICE_ID_WINBOND_82C105,
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NULL);
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lopec_ide_ports_known = 1;
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if (dev) {
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lopec_ide_regbase[0] = dev->resource[0].start;
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lopec_ide_regbase[1] = dev->resource[2].start;
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lopec_ide_ctl_regbase[0] = dev->resource[1].start;
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lopec_ide_ctl_regbase[1] = dev->resource[3].start;
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lopec_idedma_regbase = dev->resource[4].start;
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pci_dev_put(dev);
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}
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}
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static int
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lopec_ide_default_irq(unsigned long base)
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{
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if (lopec_ide_ports_known == 0)
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lopec_ide_probe();
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if (base == lopec_ide_regbase[0])
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return 14;
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else if (base == lopec_ide_regbase[1])
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return 15;
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else
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return 0;
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}
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static unsigned long
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lopec_ide_default_io_base(int index)
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{
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if (lopec_ide_ports_known == 0)
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lopec_ide_probe();
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return lopec_ide_regbase[index];
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}
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static void __init
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lopec_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data,
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unsigned long ctl, int *irq)
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{
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unsigned long reg = data;
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uint alt_status_base;
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int i;
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for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
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hw->io_ports[i] = reg++;
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if (data == lopec_ide_regbase[0]) {
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alt_status_base = lopec_ide_ctl_regbase[0] + 2;
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hw->irq = 14;
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} else if (data == lopec_ide_regbase[1]) {
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alt_status_base = lopec_ide_ctl_regbase[1] + 2;
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hw->irq = 15;
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} else {
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alt_status_base = 0;
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hw->irq = 0;
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}
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if (ctl)
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hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
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else
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hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
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if (irq != NULL)
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*irq = hw->irq;
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}
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#endif /* BLK_DEV_IDE */
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static void __init
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lopec_init_IRQ(void)
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{
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int i;
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/*
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* Provide the open_pic code with the correct table of interrupts.
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*/
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OpenPIC_InitSenses = lopec_openpic_initsenses;
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OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
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mpc10x_set_openpic();
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/* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
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openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
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&i8259_irq);
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/* Map i8259 interrupts */
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for(i = 0; i < NUM_8259_INTERRUPTS; i++)
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irq_desc[i].handler = &i8259_pic;
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/*
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* The EPIC allows for a read in the range of 0xFEF00000 ->
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* 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
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*/
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i8259_init(0xfef00000);
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}
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static int __init
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lopec_request_io(void)
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{
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outb(0x00, 0x4d0);
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outb(0xc0, 0x4d1);
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request_region(0x00, 0x20, "dma1");
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request_region(0x20, 0x20, "pic1");
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request_region(0x40, 0x20, "timer");
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request_region(0x80, 0x10, "dma page reg");
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request_region(0xa0, 0x20, "pic2");
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request_region(0xc0, 0x20, "dma2");
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return 0;
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}
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device_initcall(lopec_request_io);
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static void __init
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lopec_map_io(void)
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{
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io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
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io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
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}
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/*
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* Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
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*/
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static __inline__ void
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lopec_set_bat(void)
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{
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mb();
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mtspr(SPRN_DBAT1U, 0xf8000ffe);
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mtspr(SPRN_DBAT1L, 0xf800002a);
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mb();
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}
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TODC_ALLOC();
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static void __init
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lopec_setup_arch(void)
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{
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TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
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ioremap(0xffe80000, 0x8000), 8);
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loops_per_jiffy = 100000000/HZ;
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lopec_find_bridges();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#elif defined(CONFIG_ROOT_NFS)
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ROOT_DEV = Root_NFS;
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#elif defined(CONFIG_BLK_DEV_IDEDISK)
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ROOT_DEV = Root_HDA1;
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#else
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ROOT_DEV = Root_SDA1;
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#endif
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#ifdef CONFIG_PPCBUG_NVRAM
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/* Read in NVRAM data */
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init_prep_nvram();
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/* if no bootargs, look in NVRAM */
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if ( cmd_line[0] == '\0' ) {
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char *bootargs;
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bootargs = prep_nvram_get_var("bootargs");
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if (bootargs != NULL) {
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strcpy(cmd_line, bootargs);
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/* again.. */
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strcpy(saved_command_line, cmd_line);
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}
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}
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#endif
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}
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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lopec_set_bat();
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isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
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isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
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pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
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ISA_DMA_THRESHOLD = 0x00ffffff;
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DMA_MODE_READ = 0x44;
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DMA_MODE_WRITE = 0x48;
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ppc_md.setup_arch = lopec_setup_arch;
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ppc_md.show_cpuinfo = lopec_show_cpuinfo;
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ppc_md.irq_canonicalize = lopec_irq_canonicalize;
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ppc_md.init_IRQ = lopec_init_IRQ;
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ppc_md.get_irq = openpic_get_irq;
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ppc_md.restart = lopec_restart;
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ppc_md.power_off = lopec_power_off;
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ppc_md.halt = lopec_halt;
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ppc_md.setup_io_mappings = lopec_map_io;
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.calibrate_decr = todc_calibrate_decr;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
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ppc_ide_md.default_irq = lopec_ide_default_irq;
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ppc_ide_md.default_io_base = lopec_ide_default_io_base;
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ppc_ide_md.ide_init_hwif = lopec_ide_init_hwif_ports;
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#endif
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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ppc_md.progress = gen550_progress;
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#endif
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}
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