cec5f268cd
TPAUSE instructs the processor to enter an implementation-dependent optimized state. The instruction execution wakes up when the time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit input value. The instruction execution also wakes up due to the expiration of the operating system time-limit or by an external interrupt or exceptions such as a debug exception or a machine check exception. TPAUSE offers a choice of two lower power states: 1. Light-weight power/performance optimized state C0.1 2. Improved power/performance optimized state C0.2 This way, it can save power with low wake-up latency in comparison to spinloop based delay. The selection between the two is governed by the input register. TPAUSE is available on processors with X86_FEATURE_WAITPKG. Co-developed-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lkml.kernel.org/r/1587757076-30337-4-git-send-email-kyung.min.park@intel.com
22 lines
658 B
Plaintext
22 lines
658 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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# Copyright (C) 2020 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
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config AS_AVX512
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def_bool $(as-instr,vpmovm2b %k1$(comma)%zmm5)
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help
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Supported by binutils >= 2.25 and LLVM integrated assembler
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config AS_SHA1_NI
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def_bool $(as-instr,sha1msg1 %xmm0$(comma)%xmm1)
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help
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Supported by binutils >= 2.24 and LLVM integrated assembler
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config AS_SHA256_NI
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def_bool $(as-instr,sha256msg1 %xmm0$(comma)%xmm1)
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help
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Supported by binutils >= 2.24 and LLVM integrated assembler
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config AS_TPAUSE
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def_bool $(as-instr,tpause %ecx)
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help
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Supported by binutils >= 2.31.1 and LLVM integrated assembler >= V7
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