631dd1a885
The patch below updates broken web addresses in the kernel Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Finn Thain <fthain@telegraphics.com.au> Cc: Randy Dunlap <rdunlap@xenotime.net> Cc: Matt Turner <mattst88@gmail.com> Cc: Dimitry Torokhov <dmitry.torokhov@gmail.com> Cc: Mike Frysinger <vapier.adi@gmail.com> Acked-by: Ben Pfaff <blp@cs.stanford.edu> Acked-by: Hans J. Koch <hjk@linutronix.de> Reviewed-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
87 lines
4.0 KiB
C
87 lines
4.0 KiB
C
/*
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* Blackfin On-Chip Sport Emulated UART Driver
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*
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* Copyright 2006-2008 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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/*
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* This driver and the hardware supported are in term of EE-191 of ADI.
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* http://www.analog.com/static/imported-files/application_notes/EE191.pdf
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* This application note describe how to implement a UART on a Sharc DSP,
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* but this driver is implemented on Blackfin Processor.
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* Transmit Frame Sync is not used by this driver to transfer data out.
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*/
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#ifndef _BFIN_SPORT_UART_H
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#define _BFIN_SPORT_UART_H
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#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
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#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
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#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
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#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
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#define OFFSET_TX 0x10 /* Transmit Data Register */
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#define OFFSET_RX 0x18 /* Receive Data Register */
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#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
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#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
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#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
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#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
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#define OFFSET_STAT 0x30 /* Status Register */
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#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
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#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
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#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
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#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
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#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
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#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
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/*
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* If another interrupt fires while doing a 32-bit read from RX FIFO,
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* a fake RX underflow error will be generated. So disable interrupts
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* to prevent interruption while reading the FIFO.
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*/
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#define SPORT_GET_RX32(sport) \
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({ \
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unsigned int __ret; \
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if (ANOMALY_05000473) \
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local_irq_disable(); \
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__ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
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if (ANOMALY_05000473) \
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local_irq_enable(); \
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__ret; \
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})
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#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
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#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
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#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
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#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
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#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
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#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
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#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
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#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
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#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
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#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
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#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
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#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
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#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
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#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
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#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
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#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
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#define SPORT_TX_FIFO_SIZE 8
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#define SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin)
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#define SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
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#if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \
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|| defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \
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|| defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \
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|| defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS)
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# define CONFIG_SERIAL_BFIN_SPORT_CTSRTS
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#endif
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#endif /* _BFIN_SPORT_UART_H */
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