b69b29de65
The MCi_STATUS registers have most field definitions in common so decode them in the general path. Do not pass ecc_type along and compute it in __amd64_decode_bus_error instead. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
219 lines
5.7 KiB
C
219 lines
5.7 KiB
C
#include <linux/module.h>
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#include "edac_mce_amd.h"
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static bool report_gart_errors;
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static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
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void amd_report_gart_errors(bool v)
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{
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report_gart_errors = v;
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}
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EXPORT_SYMBOL_GPL(amd_report_gart_errors);
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void amd_register_ecc_decoder(void (*f)(int, struct err_regs *))
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{
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nb_bus_decoder = f;
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}
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EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
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void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *))
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{
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if (nb_bus_decoder) {
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WARN_ON(nb_bus_decoder != f);
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nb_bus_decoder = NULL;
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}
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}
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EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
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/*
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* string representation for the different MCA reported error types, see F3x48
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* or MSR0000_0411.
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*/
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const char *tt_msgs[] = { /* transaction type */
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"instruction",
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"data",
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"generic",
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"reserved"
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};
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EXPORT_SYMBOL_GPL(tt_msgs);
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const char *ll_msgs[] = { /* cache level */
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"L0",
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"L1",
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"L2",
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"L3/generic"
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};
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EXPORT_SYMBOL_GPL(ll_msgs);
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const char *rrrr_msgs[] = {
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"generic",
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"generic read",
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"generic write",
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"data read",
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"data write",
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"inst fetch",
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"prefetch",
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"evict",
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"snoop",
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"reserved RRRR= 9",
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"reserved RRRR= 10",
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"reserved RRRR= 11",
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"reserved RRRR= 12",
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"reserved RRRR= 13",
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"reserved RRRR= 14",
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"reserved RRRR= 15"
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};
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EXPORT_SYMBOL_GPL(rrrr_msgs);
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const char *pp_msgs[] = { /* participating processor */
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"local node originated (SRC)",
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"local node responded to request (RES)",
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"local node observed as 3rd party (OBS)",
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"generic"
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};
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EXPORT_SYMBOL_GPL(pp_msgs);
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const char *to_msgs[] = {
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"no timeout",
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"timed out"
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};
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EXPORT_SYMBOL_GPL(to_msgs);
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const char *ii_msgs[] = { /* memory or i/o */
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"mem access",
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"reserved",
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"i/o access",
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"generic"
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};
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EXPORT_SYMBOL_GPL(ii_msgs);
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/*
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* Map the 4 or 5 (family-specific) bits of Extended Error code to the
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* string table.
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*/
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const char *ext_msgs[] = {
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"K8 ECC error", /* 0_0000b */
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"CRC error on link", /* 0_0001b */
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"Sync error packets on link", /* 0_0010b */
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"Master Abort during link operation", /* 0_0011b */
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"Target Abort during link operation", /* 0_0100b */
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"Invalid GART PTE entry during table walk", /* 0_0101b */
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"Unsupported atomic RMW command received", /* 0_0110b */
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"WDT error: NB transaction timeout", /* 0_0111b */
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"ECC/ChipKill ECC error", /* 0_1000b */
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"SVM DEV Error", /* 0_1001b */
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"Link Data error", /* 0_1010b */
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"Link/L3/Probe Filter Protocol error", /* 0_1011b */
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"NB Internal Arrays Parity error", /* 0_1100b */
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"DRAM Address/Control Parity error", /* 0_1101b */
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"Link Transmission error", /* 0_1110b */
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"GART/DEV Table Walk Data error" /* 0_1111b */
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"Res 0x100 error", /* 1_0000b */
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"Res 0x101 error", /* 1_0001b */
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"Res 0x102 error", /* 1_0010b */
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"Res 0x103 error", /* 1_0011b */
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"Res 0x104 error", /* 1_0100b */
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"Res 0x105 error", /* 1_0101b */
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"Res 0x106 error", /* 1_0110b */
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"Res 0x107 error", /* 1_0111b */
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"Res 0x108 error", /* 1_1000b */
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"Res 0x109 error", /* 1_1001b */
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"Res 0x10A error", /* 1_1010b */
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"Res 0x10B error", /* 1_1011b */
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"ECC error in L3 Cache Data", /* 1_1100b */
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"L3 Cache Tag error", /* 1_1101b */
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"L3 Cache LRU Parity error", /* 1_1110b */
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"Probe Filter error" /* 1_1111b */
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};
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EXPORT_SYMBOL_GPL(ext_msgs);
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void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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{
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u32 ec = ERROR_CODE(regs->nbsl);
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u32 xec = EXT_ERROR_CODE(regs->nbsl);
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if (!handle_errors)
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return;
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pr_emerg(" Northbridge Error, node %d", node_id);
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/*
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* F10h, revD can disable ErrCpu[3:0] so check that first and also the
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* value encoding has changed so interpret those differently
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*/
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if ((boot_cpu_data.x86 == 0x10) &&
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(boot_cpu_data.x86_model > 8)) {
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if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
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pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
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} else {
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pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
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}
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if (TLB_ERROR(ec)) {
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/*
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* GART errors are intended to help graphics driver developers
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* to detect bad GART PTEs. It is recommended by AMD to disable
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* GART table walk error reporting by default[1] (currently
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* being disabled in mce_cpu_quirks()) and according to the
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* comment in mce_cpu_quirks(), such GART errors can be
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* incorrectly triggered. We may see these errors anyway and
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* unless requested by the user, they won't be reported.
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*
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* [1] section 13.10.1 on BIOS and Kernel Developers Guide for
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* AMD NPT family 0Fh processors
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*/
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if (!report_gart_errors)
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return;
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pr_emerg(" GART TLB error, Transaction: %s, Cache Level %s\n",
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TT_MSG(ec), LL_MSG(ec));
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} else if (MEM_ERROR(ec)) {
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pr_emerg(" Memory/Cache error, Transaction: %s, Type: %s,"
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" Cache Level: %s",
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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} else if (BUS_ERROR(ec)) {
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pr_emerg(" Bus (Link/DRAM) error\n");
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if (nb_bus_decoder)
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nb_bus_decoder(node_id, regs);
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} else {
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/* shouldn't reach here! */
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pr_warning("%s: unknown MCE error 0x%x\n", __func__, ec);
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}
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pr_emerg("%s.\n", EXT_ERR_MSG(xec));
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}
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EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
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void decode_mce(struct mce *m)
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{
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struct err_regs regs;
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int node, ecc;
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pr_emerg("MC%d_STATUS:\n", m->bank);
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pr_emerg(" Error: %sorrected, Report: %s, MiscV: %svalid, "
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"CPU context corrupt: %s",
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((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
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((m->status & MCI_STATUS_EN) ? "yes" : "no"),
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((m->status & MCI_STATUS_MISCV) ? "" : "in"),
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((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
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/* do the two bits[14:13] together */
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ecc = m->status & (3ULL << 45);
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if (ecc)
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pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
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pr_cont("\n");
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if (m->bank == 4) {
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regs.nbsl = (u32) m->status;
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regs.nbsh = (u32)(m->status >> 32);
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regs.nbeal = (u32) m->addr;
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regs.nbeah = (u32)(m->addr >> 32);
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node = per_cpu(cpu_llc_id, m->extcpu);
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amd_decode_nb_mce(node, ®s, 1);
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}
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}
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