Santosh Shilimkar b9e0d40c0d clk: keystone: add Keystone PLL clock driver ... Add the driver for the PLL IPs found on Keystone 2 devices. The PLL IP typically has a multiplier, a divider and a post-divider. The PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main PLL is controlled by a PLL controller and memory map registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2013-10-07 18:16:21 -07:00
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pll.c	clk: keystone: add Keystone PLL clock driver	2013-10-07 18:16:21 -07:00