bb579cf1d4
A find -iname \*.[ch] | xargs grep "> ARRAY_SIZE(" revealed several
incorrect usages of ARRAY_SIZE in the mpc drivers. The last element in the
array is always ARRAY_SIZE()-1, this patch modifies the bounds checks
accordingly.
Signed-off-by: Eric Sesterhenn <snakebyte@gmx.de>
Cc: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
477 lines
12 KiB
C
477 lines
12 KiB
C
/*arch/ppc/platforms/mpc885ads_setup.c
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*
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* Platform setup for the Freescale mpc885ads board
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*
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* Copyright 2005 MontaVista Software Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/fs_enet_pd.h>
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#include <linux/fs_uart_pd.h>
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#include <linux/mii.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/ppcboot.h>
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#include <asm/8xx_immap.h>
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#include <asm/commproc.h>
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#include <asm/ppc_sys.h>
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extern unsigned char __res[];
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static void setup_smc1_ioports(void);
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static void setup_smc2_ioports(void);
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static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
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static void setup_fec1_ioports(void);
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static void setup_fec2_ioports(void);
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static void setup_scc3_ioports(void);
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static struct fs_uart_platform_info mpc885_uart_pdata[] = {
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[fsid_smc1_uart] = {
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.brg = 1,
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.fs_no = fsid_smc1_uart,
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.init_ioports = setup_smc1_ioports,
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.tx_num_fifo = 4,
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.tx_buf_size = 32,
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.rx_num_fifo = 4,
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.rx_buf_size = 32,
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},
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[fsid_smc2_uart] = {
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.brg = 2,
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.fs_no = fsid_smc2_uart,
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.init_ioports = setup_smc2_ioports,
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.tx_num_fifo = 4,
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.tx_buf_size = 32,
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.rx_num_fifo = 4,
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.rx_buf_size = 32,
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},
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};
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static struct fs_platform_info mpc8xx_enet_pdata[] = {
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[fsid_fec1] = {
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.rx_ring = 128,
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.tx_ring = 16,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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.init_ioports = setup_fec1_ioports,
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.bus_id = "0:00",
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.has_phy = 1,
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},
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[fsid_fec2] = {
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.rx_ring = 128,
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.tx_ring = 16,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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.init_ioports = setup_fec2_ioports,
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.bus_id = "0:01",
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.has_phy = 1,
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},
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[fsid_scc3] = {
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.rx_ring = 64,
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.tx_ring = 8,
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.rx_copybreak = 240,
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.use_napi = 1,
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.napi_weight = 17,
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.init_ioports = setup_scc3_ioports,
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#ifdef CONFIG_FIXED_MII_10_FDX
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.bus_id = "fixed@100:1",
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#else
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.bus_id = "0:02",
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#endif
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},
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};
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void __init board_init(void)
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{
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cpm8xx_t *cp = cpmp;
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unsigned int *bcsr_io;
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#ifdef CONFIG_FS_ENET
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immap_t *immap = (immap_t *) IMAP_ADDR;
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#endif
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR\n");
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return;
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}
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#ifdef CONFIG_SERIAL_CPM_SMC1
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cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
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clrbits32(bcsr_io, BCSR1_RS232EN_1);
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cp->cp_smc[0].smc_smcm |= (SMCM_RX | SMCM_TX);
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cp->cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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#else
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setbits32(bcsr_io,BCSR1_RS232EN_1);
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cp->cp_smc[0].smc_smcmr = 0;
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cp->cp_smc[0].smc_smce = 0;
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#endif
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#ifdef CONFIG_SERIAL_CPM_SMC2
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cp->cp_simode &= ~(0xe0000000 >> 1);
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cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
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clrbits32(bcsr_io,BCSR1_RS232EN_2);
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cp->cp_smc[1].smc_smcm |= (SMCM_RX | SMCM_TX);
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cp->cp_smc[1].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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#else
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setbits32(bcsr_io,BCSR1_RS232EN_2);
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cp->cp_smc[1].smc_smcmr = 0;
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cp->cp_smc[1].smc_smce = 0;
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#endif
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iounmap(bcsr_io);
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#ifdef CONFIG_FS_ENET
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/* use MDC for MII (common) */
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setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
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clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
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bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
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clrbits32(bcsr_io,BCSR5_MII1_EN);
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clrbits32(bcsr_io,BCSR5_MII1_RST);
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#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
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clrbits32(bcsr_io,BCSR5_MII2_EN);
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clrbits32(bcsr_io,BCSR5_MII2_RST);
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#endif
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iounmap(bcsr_io);
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#endif
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}
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static void setup_fec1_ioports(struct fs_platform_info*)
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{
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immap_t *immap = (immap_t *) IMAP_ADDR;
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/* configure FEC1 pins */
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setbits16(&immap->im_ioport.iop_papar, 0xf830);
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setbits16(&immap->im_ioport.iop_padir, 0x0830);
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clrbits16(&immap->im_ioport.iop_padir, 0xf000);
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setbits32(&immap->im_cpm.cp_pbpar, 0x00001001);
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clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001);
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setbits16(&immap->im_ioport.iop_pcpar, 0x000c);
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clrbits16(&immap->im_ioport.iop_pcdir, 0x000c);
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setbits32(&immap->im_cpm.cp_pepar, 0x00000003);
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setbits32(&immap->im_cpm.cp_pedir, 0x00000003);
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clrbits32(&immap->im_cpm.cp_peso, 0x00000003);
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clrbits32(&immap->im_cpm.cp_cptr, 0x00000100);
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}
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static void setup_fec2_ioports(struct fs_platform_info*)
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{
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immap_t *immap = (immap_t *) IMAP_ADDR;
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/* configure FEC2 pins */
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setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
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setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
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clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
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setbits32(&immap->im_cpm.cp_peso, 0x00037800);
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clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
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}
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static void setup_scc3_ioports(struct fs_platform_info*)
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{
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immap_t *immap = (immap_t *) IMAP_ADDR;
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unsigned *bcsr_io;
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bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR\n");
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return;
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}
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/* Enable the PHY.
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*/
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clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
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udelay(1000);
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setbits32(bcsr_io+4, BCSR4_ETH10_RST);
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/* Configure port A pins for Txd and Rxd.
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*/
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setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
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clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
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/* Configure port C pins to enable CLSN and RENA.
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*/
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clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
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clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
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setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
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/* Configure port E for TCLK and RCLK.
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*/
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setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
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clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
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clrbits32(&immap->im_cpm.cp_pedir,
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PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
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clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
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setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
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/* Configure Serial Interface clock routing.
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* First, clear all SCC bits to zero, then set the ones we want.
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*/
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clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
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setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
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/* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
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*/
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immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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/* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
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* by H/W setting after reset. SCC ethernet controller support only half duplex.
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* This discrepancy of modes causes a lot of carrier lost errors.
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*/
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/* In the original SCC enet driver the following code is placed at
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the end of the initialization */
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setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
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clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
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setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
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setbits32(bcsr_io+4, BCSR1_ETHEN);
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iounmap(bcsr_io);
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}
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static int mac_count = 0;
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static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
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{
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struct fs_platform_info *fpi;
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bd_t *bd = (bd_t *) __res;
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char *e;
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int i;
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if(fs_no >= ARRAY_SIZE(mpc8xx_enet_pdata)) {
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printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
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return;
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}
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fpi = &mpc8xx_enet_pdata[fs_no];
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switch (fs_no) {
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case fsid_fec1:
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fpi->init_ioports = &setup_fec1_ioports;
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break;
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case fsid_fec2:
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fpi->init_ioports = &setup_fec2_ioports;
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break;
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case fsid_scc3:
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fpi->init_ioports = &setup_scc3_ioports;
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break;
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default:
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printk(KERN_WARNING "Device %s is not supported!\n", pdev->name);
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return;
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}
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pdev->dev.platform_data = fpi;
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fpi->fs_no = fs_no;
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e = (unsigned char *)&bd->bi_enetaddr;
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for (i = 0; i < 6; i++)
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fpi->macaddr[i] = *e++;
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fpi->macaddr[5] += mac_count++;
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}
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static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev,
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int idx)
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{
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/* This is for FEC devices only */
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if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
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return;
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mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
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}
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static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
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int idx)
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{
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/* This is for SCC devices only */
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if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
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return;
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mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
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}
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static void setup_smc1_ioports(struct fs_uart_platform_info*)
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{
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immap_t *immap = (immap_t *) IMAP_ADDR;
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unsigned *bcsr_io;
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unsigned int iobits = 0x000000c0;
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR1\n");
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return;
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}
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clrbits32(bcsr_io,BCSR1_RS232EN_1);
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iounmap(bcsr_io);
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setbits32(&immap->im_cpm.cp_pbpar, iobits);
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clrbits32(&immap->im_cpm.cp_pbdir, iobits);
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clrbits16(&immap->im_cpm.cp_pbodr, iobits);
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}
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static void setup_smc2_ioports(struct fs_uart_platform_info*)
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{
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immap_t *immap = (immap_t *) IMAP_ADDR;
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unsigned *bcsr_io;
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unsigned int iobits = 0x00000c00;
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bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (bcsr_io == NULL) {
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printk(KERN_CRIT "Could not remap BCSR1\n");
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return;
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}
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clrbits32(bcsr_io,BCSR1_RS232EN_2);
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iounmap(bcsr_io);
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#ifndef CONFIG_SERIAL_CPM_ALT_SMC2
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setbits32(&immap->im_cpm.cp_pbpar, iobits);
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clrbits32(&immap->im_cpm.cp_pbdir, iobits);
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clrbits16(&immap->im_cpm.cp_pbodr, iobits);
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#else
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setbits16(&immap->im_ioport.iop_papar, iobits);
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clrbits16(&immap->im_ioport.iop_padir, iobits);
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clrbits16(&immap->im_ioport.iop_paodr, iobits);
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#endif
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}
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static void __init mpc885ads_fixup_uart_pdata(struct platform_device *pdev,
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int idx)
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{
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bd_t *bd = (bd_t *) __res;
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struct fs_uart_platform_info *pinfo;
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int num = ARRAY_SIZE(mpc885_uart_pdata);
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int id = fs_uart_id_smc2fsid(idx);
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/* no need to alter anything if console */
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if ((id < num) && (!pdev->dev.platform_data)) {
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pinfo = &mpc885_uart_pdata[id];
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pinfo->uart_clk = bd->bi_intfreq;
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pdev->dev.platform_data = pinfo;
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}
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}
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static int mpc885ads_platform_notify(struct device *dev)
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{
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static const struct platform_notify_dev_map dev_map[] = {
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{
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.bus_id = "fsl-cpm-fec",
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.rtn = mpc885ads_fixup_fec_enet_pdata,
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},
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{
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.bus_id = "fsl-cpm-scc",
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.rtn = mpc885ads_fixup_scc_enet_pdata,
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},
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{
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.bus_id = "fsl-cpm-smc:uart",
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.rtn = mpc885ads_fixup_uart_pdata
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},
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{
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.bus_id = NULL
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}
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};
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platform_notify_map(dev_map,dev);
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return 0;
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}
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int __init mpc885ads_init(void)
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{
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struct fs_mii_fec_platform_info* fmpi;
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bd_t *bd = (bd_t *) __res;
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printk(KERN_NOTICE "mpc885ads: Init\n");
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platform_notify = mpc885ads_platform_notify;
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ppc_sys_device_initfunc();
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ppc_sys_device_disable_all();
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ppc_sys_device_enable(MPC8xx_CPM_FEC1);
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ppc_sys_device_enable(MPC8xx_MDIO_FEC);
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fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
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&mpc8xx_mdio_fec_pdata;
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fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
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/* No PHY interrupt line here */
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fmpi->irq[0xf] = SIU_IRQ7;
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#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
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ppc_sys_device_enable(MPC8xx_CPM_SCC3);
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#endif
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#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
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ppc_sys_device_enable(MPC8xx_CPM_FEC2);
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#endif
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#ifdef CONFIG_SERIAL_CPM_SMC1
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ppc_sys_device_enable(MPC8xx_CPM_SMC1);
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ppc_sys_device_setfunc(MPC8xx_CPM_SMC1, PPC_SYS_FUNC_UART);
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#endif
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|
|
|
#ifdef CONFIG_SERIAL_CPM_SMC2
|
|
ppc_sys_device_enable(MPC8xx_CPM_SMC2);
|
|
ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(mpc885ads_init);
|
|
|
|
/*
|
|
To prevent confusion, console selection is gross:
|
|
by 0 assumed SMC1 and by 1 assumed SMC2
|
|
*/
|
|
struct platform_device* early_uart_get_pdev(int index)
|
|
{
|
|
bd_t *bd = (bd_t *) __res;
|
|
struct fs_uart_platform_info *pinfo;
|
|
|
|
struct platform_device* pdev = NULL;
|
|
if(index) { /*assume SMC2 here*/
|
|
pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC2];
|
|
pinfo = &mpc885_uart_pdata[1];
|
|
} else { /*over SMC1*/
|
|
pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC1];
|
|
pinfo = &mpc885_uart_pdata[0];
|
|
}
|
|
|
|
pinfo->uart_clk = bd->bi_intfreq;
|
|
pdev->dev.platform_data = pinfo;
|
|
ppc_sys_fixup_mem_resource(pdev, IMAP_ADDR);
|
|
return NULL;
|
|
}
|
|
|