23b5e15a29
Add mxs specific clocks, pll, reference clock (PFD), integer divider and fractional divider. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
155 lines
3.3 KiB
C
155 lines
3.3 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_ref - mxs reference clock
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* @hw: clk_hw for the reference clock
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* @reg: register address
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* @idx: the index of the reference clock within the same register
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*
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* The mxs reference clock sources from pll. Every 4 reference clocks share
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* one register space, and @idx is used to identify them. Each reference
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* clock has a gate control and a fractional * divider. The rate is calculated
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* as pll rate * (18 / FRAC), where FRAC = 18 ~ 35.
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*/
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struct clk_ref {
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struct clk_hw hw;
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void __iomem *reg;
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u8 idx;
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};
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#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw)
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static int clk_ref_enable(struct clk_hw *hw)
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{
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struct clk_ref *ref = to_clk_ref(hw);
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writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
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return 0;
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}
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static void clk_ref_disable(struct clk_hw *hw)
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{
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struct clk_ref *ref = to_clk_ref(hw);
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writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
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}
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static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_ref *ref = to_clk_ref(hw);
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u64 tmp = parent_rate;
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u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f;
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tmp *= 18;
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do_div(tmp, frac);
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return tmp;
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}
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static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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u64 tmp = parent_rate;
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u8 frac;
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tmp = tmp * 18 + rate / 2;
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do_div(tmp, rate);
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frac = tmp;
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if (frac < 18)
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frac = 18;
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else if (frac > 35)
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frac = 35;
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tmp = parent_rate;
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tmp *= 18;
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do_div(tmp, frac);
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return tmp;
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}
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static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_ref *ref = to_clk_ref(hw);
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unsigned long flags;
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u64 tmp = parent_rate;
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u32 val;
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u8 frac, shift = ref->idx * 8;
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tmp = tmp * 18 + rate / 2;
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do_div(tmp, rate);
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frac = tmp;
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if (frac < 18)
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frac = 18;
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else if (frac > 35)
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frac = 35;
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spin_lock_irqsave(&mxs_lock, flags);
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val = readl_relaxed(ref->reg);
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val &= ~(0x3f << shift);
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val |= frac << shift;
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writel_relaxed(val, ref->reg);
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spin_unlock_irqrestore(&mxs_lock, flags);
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return 0;
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}
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static const struct clk_ops clk_ref_ops = {
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.enable = clk_ref_enable,
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.disable = clk_ref_disable,
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.recalc_rate = clk_ref_recalc_rate,
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.round_rate = clk_ref_round_rate,
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.set_rate = clk_ref_set_rate,
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};
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struct clk *mxs_clk_ref(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx)
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{
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struct clk_ref *ref;
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struct clk *clk;
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struct clk_init_data init;
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ref = kzalloc(sizeof(*ref), GFP_KERNEL);
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if (!ref)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_ref_ops;
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init.flags = 0;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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ref->reg = reg;
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ref->idx = idx;
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ref->hw.init = &init;
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clk = clk_register(NULL, &ref->hw);
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if (IS_ERR(clk))
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kfree(ref);
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return clk;
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}
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