bac4e960b5
Mathieu Desnoyers pointed out that the ARM barriers were lacking: - cmpxchg, xchg and atomic add return need memory barriers on architectures which can reorder the relative order in which memory read/writes can be seen between CPUs, which seems to include recent ARM architectures. Those barriers are currently missing on ARM. - test_and_xxx_bit were missing SMP barriers. So put these barriers in. Provide separate atomic_add/atomic_sub operations which do not require barriers. Reported-Reviewed-and-Acked-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
||
|---|---|---|
| .. | ||
| ashldi3.S | ||
| ashrdi3.S | ||
| backtrace.S | ||
| bitops.h | ||
| changebit.S | ||
| clear_user.S | ||
| clearbit.S | ||
| copy_from_user.S | ||
| copy_page.S | ||
| copy_template.S | ||
| copy_to_user.S | ||
| csumipv6.S | ||
| csumpartial.S | ||
| csumpartialcopy.S | ||
| csumpartialcopygeneric.S | ||
| csumpartialcopyuser.S | ||
| delay.S | ||
| div64.S | ||
| ecard.S | ||
| findbit.S | ||
| floppydma.S | ||
| getuser.S | ||
| io-acorn.S | ||
| io-readsb.S | ||
| io-readsl.S | ||
| io-readsw-armv3.S | ||
| io-readsw-armv4.S | ||
| io-shark.c | ||
| io-writesb.S | ||
| io-writesl.S | ||
| io-writesw-armv3.S | ||
| io-writesw-armv4.S | ||
| lib1funcs.S | ||
| lshrdi3.S | ||
| Makefile | ||
| memchr.S | ||
| memcpy.S | ||
| memmove.S | ||
| memset.S | ||
| memzero.S | ||
| muldi3.S | ||
| putuser.S | ||
| setbit.S | ||
| sha1.S | ||
| strchr.S | ||
| strncpy_from_user.S | ||
| strnlen_user.S | ||
| strrchr.S | ||
| testchangebit.S | ||
| testclearbit.S | ||
| testsetbit.S | ||
| uaccess.S | ||
| ucmpdi2.S | ||