916f562fb2
side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1 -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl0uBEERHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSWucw/9ELKlfvdxrc8mdIuzt+CpKdNiSG88shXY hF+vnuE6Jhv5hmlbA/DbplPTAnHT/FQF65/GPQMAYy2wYO6CjleNxQyepiVv4h8/ tWoXu5vYZXubtQyMnYTffREzjYFPBNAscLUhXNwJKRno7nT0qKCk62WgOMfaW/KN lP5dKmrL7rdJDUvxHEStrwP515Lg5Wkhj3+XzgbgFUKGuGlvHfwUOEZucT++kqhu Z1vMjPv2ksHQf3r15BsbX/6jMIONEt2Xd6jA3Lm7ebDXJl2hjX4Gq0Kkl5pmkj2w F0V7Tw4XYk6DkSl7HQaOBgQ8KV0Mw2L8Vj6eEDhUwx6wPGlQ5YTKkUCJkjs0mUyb UpO3TuPFN2W0hsTNDzwYpjqcfodDn159XJcduv1/ZpIanUvHgx0uVzQ7iwwYwW+l VR4SipY5AEn9hpief30X7TAUSKsE4do58imYeoGBrq78zdsJaEcDAMX7AcYdXVQ9 ahBS8ME/d1JEBNdRsSW7eTAfu8dZdI08uR8/T37GRG59XyZSjsyVmZ6kHCYrBygF AyLNMsXMCbW1rOoIpWkuGMD86XZy40laLg8T7WWTaq28t1VQ0BaBTGM4/eEexs3p FhZ1M7aH+PsDLrI2IGTBt/4xAMv+dhDS7HnxRlOONbWnLWVqmR+tYzF0aCkqJCmd O2zWCGffeYs= =mK0C -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
245 lines
5.6 KiB
C
245 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Ingenic JZ4740 SoC CGU driver
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*
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* Copyright (c) 2015 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/jz4740-cgu.h>
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#include "cgu.h"
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#include "pm.h"
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/* CGU register offsets */
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#define CGU_REG_CPCCR 0x00
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#define CGU_REG_LCR 0x04
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#define CGU_REG_CPPCR 0x10
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#define CGU_REG_CLKGR 0x20
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#define CGU_REG_SCR 0x24
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#define CGU_REG_I2SCDR 0x60
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#define CGU_REG_LPCDR 0x64
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#define CGU_REG_MSCCDR 0x68
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#define CGU_REG_UHCCDR 0x6c
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#define CGU_REG_SSICDR 0x74
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/* bits within a PLL control register */
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#define PLLCTL_M_SHIFT 23
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#define PLLCTL_M_MASK (0x1ff << PLLCTL_M_SHIFT)
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#define PLLCTL_N_SHIFT 18
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#define PLLCTL_N_MASK (0x1f << PLLCTL_N_SHIFT)
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#define PLLCTL_OD_SHIFT 16
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#define PLLCTL_OD_MASK (0x3 << PLLCTL_OD_SHIFT)
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#define PLLCTL_STABLE (1 << 10)
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#define PLLCTL_BYPASS (1 << 9)
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#define PLLCTL_ENABLE (1 << 8)
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/* bits within the LCR register */
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#define LCR_SLEEP (1 << 0)
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/* bits within the CLKGR register */
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#define CLKGR_UDC (1 << 11)
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static struct ingenic_cgu *cgu;
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static const s8 pll_od_encoding[4] = {
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0x0, 0x1, -1, 0x3,
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};
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static const u8 jz4740_cgu_cpccr_div_table[] = {
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1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
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};
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static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
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/* External clocks */
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[JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
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[JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
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[JZ4740_CLK_PLL] = {
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"pll", CGU_CLK_PLL,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.pll = {
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.reg = CGU_REG_CPPCR,
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.m_shift = 23,
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.m_bits = 9,
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.m_offset = 2,
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.n_shift = 18,
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.n_bits = 5,
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.n_offset = 2,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 4,
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.od_encoding = pll_od_encoding,
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.stable_bit = 10,
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.bypass_bit = 9,
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.enable_bit = 8,
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},
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},
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/* Muxes & dividers */
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[JZ4740_CLK_PLL_HALF] = {
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"pll half", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
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},
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[JZ4740_CLK_CCLK] = {
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"cclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = {
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CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
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jz4740_cgu_cpccr_div_table,
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},
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},
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[JZ4740_CLK_HCLK] = {
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"hclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = {
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CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
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jz4740_cgu_cpccr_div_table,
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},
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},
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[JZ4740_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = {
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CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
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jz4740_cgu_cpccr_div_table,
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},
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},
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[JZ4740_CLK_MCLK] = {
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"mclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = {
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CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
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jz4740_cgu_cpccr_div_table,
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},
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},
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[JZ4740_CLK_LCD] = {
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"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = {
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CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1,
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jz4740_cgu_cpccr_div_table,
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},
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.gate = { CGU_REG_CLKGR, 10 },
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},
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[JZ4740_CLK_LCD_PCLK] = {
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"lcd_pclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
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},
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[JZ4740_CLK_I2S] = {
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"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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.mux = { CGU_REG_CPCCR, 31, 1 },
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.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 6 },
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},
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[JZ4740_CLK_SPI] = {
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"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
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.mux = { CGU_REG_SSICDR, 31, 1 },
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.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 4 },
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},
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[JZ4740_CLK_MMC] = {
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"mmc", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 7 },
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},
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[JZ4740_CLK_UHC] = {
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"uhc", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 14 },
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},
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[JZ4740_CLK_UDC] = {
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"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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.mux = { CGU_REG_CPCCR, 29, 1 },
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.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
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.gate = { CGU_REG_SCR, 6, true },
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},
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/* Gate-only clocks */
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[JZ4740_CLK_UART0] = {
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"uart0", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 0 },
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},
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[JZ4740_CLK_UART1] = {
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"uart1", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 15 },
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},
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[JZ4740_CLK_DMA] = {
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"dma", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 12 },
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},
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[JZ4740_CLK_IPU] = {
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"ipu", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 13 },
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},
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[JZ4740_CLK_ADC] = {
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"adc", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 8 },
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},
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[JZ4740_CLK_I2C] = {
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"i2c", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 3 },
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},
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[JZ4740_CLK_AIC] = {
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"aic", CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 5 },
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},
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};
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static void __init jz4740_cgu_init(struct device_node *np)
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{
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int retval;
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cgu = ingenic_cgu_new(jz4740_cgu_clocks,
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ARRAY_SIZE(jz4740_cgu_clocks), np);
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if (!cgu) {
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pr_err("%s: failed to initialise CGU\n", __func__);
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return;
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}
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retval = ingenic_cgu_register_clocks(cgu);
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if (retval)
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pr_err("%s: failed to register CGU Clocks\n", __func__);
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ingenic_cgu_register_syscore_ops(cgu);
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}
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CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
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