cb3ac5947a
Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
44 lines
733 B
C
44 lines
733 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <asm/div64.h>
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#include "clk.h"
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#define div_mask(w) ((1 << (w)) - 1)
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int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
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u8 frac_width, u8 flags)
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{
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u64 divider_ux1 = parent_rate;
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int mul;
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if (!rate)
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return 0;
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mul = 1 << frac_width;
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if (!(flags & TEGRA_DIVIDER_INT))
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divider_ux1 *= mul;
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if (flags & TEGRA_DIVIDER_ROUND_UP)
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divider_ux1 += rate - 1;
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do_div(divider_ux1, rate);
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if (flags & TEGRA_DIVIDER_INT)
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divider_ux1 *= mul;
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if (divider_ux1 < mul)
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return 0;
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divider_ux1 -= mul;
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if (divider_ux1 > div_mask(width))
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return div_mask(width);
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return divider_ux1;
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}
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