3f06962273
MTD core changes: - New Hyperbus framework - New _is_locked (concat) implementation - Various cleanups NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: * fix BCH ECC layout for large page NAND parts * fallback to detected ecc-strength, ecc-step-size * when oops in progress use pio and interrupt polling * code refactor code to introduce helper functions * add support for v7.3 controller - FSMC: * use nand_op_trace for operation tracing - GPMI: * move all driver code into single file * various cleanups (including dmaengine changes) * use runtime PM to manage clocks * implement exec_op - MTK: * correct low level time calculation of r/w cycle * improve data sampling timing for read cycle * add validity check for CE# pin setting * fix wrongly assigned OOB buffer pointer issue * re-license MTK NAND driver as Dual MIT/GPL - STM32: * manage the get_irq error case * increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAl0qLr4ACgkQJWrqGEe9 VoQVCwf/ZCG5CldS3cs6B68kMJoZ/rJyJxBnxtIhffda2vw1KG/12o6XaDO9xA/R EwYrOTzlYZxzCZsNvWyHepG3Kj3d38CJ52ZqhavjpihwMlKKOgW/K39xuKWCrfxS sVMLz/UdrcsQfcPGAy7DSyqhzRAtupNxngCdEkIIMGFZWsv4uZfOFEGMrzUJ5RYN /okIyUE7Iz0dRq1/KXSl365V1MS8QP2eHFuHrUd38+kJ8TJnQjXX3Bmdul4aNTx+ HIIpykovoAn5BZ0YA4lJL90zVoDOWysARwHIAMDvJa8zS0wDTU16Tj2M6AQK+a4x hbIOOkeX0hTKpJvy7/khli5y1bn2mw== =L+tV -----END PGP SIGNATURE----- Merge tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "This contains the following changes for MTD: MTD core changes: - New Hyperbus framework - New _is_locked (concat) implementation - Various cleanups NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: - fix BCH ECC layout for large page NAND parts - fallback to detected ecc-strength, ecc-step-size - when oops in progress use pio and interrupt polling - code refactor code to introduce helper functions - add support for v7.3 controller - FSMC: - use nand_op_trace for operation tracing - GPMI: - move all driver code into single file - various cleanups (including dmaengine changes) - use runtime PM to manage clocks - implement exec_op - MTK: - correct low level time calculation of r/w cycle - improve data sampling timing for read cycle - add validity check for CE# pin setting - fix wrongly assigned OOB buffer pointer issue - re-license MTK NAND driver as Dual MIT/GPL - STM32: - manage the get_irq error case - increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control" * tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (60 commits) mtd: concat: implement _is_locked mtd operation mtd: concat: refactor concat_lock/concat_unlock mtd: abi: do not use C++ style comments in uapi header mtd: afs: remove unneeded NULL check mtd: rawnand: stm32_fmc2: increase DMA completion timeouts mtd: rawnand: Use kzalloc() instead of kmalloc() and memset() mtd: hyperbus: Add driver for TI's HyperBus memory controller mtd: spinand: read returns badly if the last page has bitflips mtd: spinand: Add initial support for Paragon PN26G0xA mtd: rawnand: mtk: Re-license MTK NAND driver as Dual MIT/GPL mtd: rawnand: gpmi: remove double assignment to block_size dt-bindings: mtd: brcmnand: Add brcmnand, brcmnand-v7.3 support mtd: rawnand: brcmnand: Add support for v7.3 controller mtd: rawnand: brcmnand: Refactored code to introduce helper functions mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling mtd: Add flag to indicate panic_write mtd: rawnand: Add Macronix NAND read retry support mtd: onenand: Avoid fall-through warnings mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG mtd: spinand: Add support for two-byte device IDs ...
86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel PCH/PCU SPI flash PCI driver.
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*
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* Copyright (C) 2016, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "intel-spi.h"
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#define BCR 0xdc
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#define BCR_WPD BIT(0)
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static const struct intel_spi_boardinfo bxt_info = {
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.type = INTEL_SPI_BXT,
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};
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static int intel_spi_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct intel_spi_boardinfo *info;
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struct intel_spi *ispi;
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u32 bcr;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
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GFP_KERNEL);
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if (!info)
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return -ENOMEM;
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/* Try to make the chip read/write */
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pci_read_config_dword(pdev, BCR, &bcr);
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if (!(bcr & BCR_WPD)) {
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bcr |= BCR_WPD;
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pci_write_config_dword(pdev, BCR, bcr);
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pci_read_config_dword(pdev, BCR, &bcr);
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}
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info->writeable = !!(bcr & BCR_WPD);
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ispi = intel_spi_probe(&pdev->dev, &pdev->resource[0], info);
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if (IS_ERR(ispi))
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return PTR_ERR(ispi);
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pci_set_drvdata(pdev, ispi);
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return 0;
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}
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static void intel_spi_pci_remove(struct pci_dev *pdev)
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{
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intel_spi_remove(pci_get_drvdata(pdev));
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}
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static const struct pci_device_id intel_spi_pci_ids[] = {
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{ PCI_VDEVICE(INTEL, 0x02a4), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0x18e0), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0x19e0), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0x34a4), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0x4b24), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info },
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{ PCI_VDEVICE(INTEL, 0xa224), (unsigned long)&bxt_info },
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{ },
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};
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MODULE_DEVICE_TABLE(pci, intel_spi_pci_ids);
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static struct pci_driver intel_spi_pci_driver = {
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.name = "intel-spi",
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.id_table = intel_spi_pci_ids,
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.probe = intel_spi_pci_probe,
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.remove = intel_spi_pci_remove,
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};
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module_pci_driver(intel_spi_pci_driver);
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MODULE_DESCRIPTION("Intel PCH/PCU SPI flash PCI driver");
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MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
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MODULE_LICENSE("GPL v2");
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