1948d5c51d
Intel Lightning Mountain SoC has a pinmux controller & GPIO controller IP which controls pin multiplexing & configuration including GPIO functions selection & GPIO attributes configuration. This IP is not based on & does not have anything in common with Chassis specification. The pinctrl drivers under pinctrl/intel/* are all based upon Chassis spec compliant pinctrl IPs. So this driver doesn't fit & can not use pinctrl framework under pinctrl/intel/* and it requires a separate new driver. Add a new GPIO & pin control framework based driver for this IP. Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Link: https://lore.kernel.org/r/33e649758b70490f01724a887c490d5008c7656d.1573797249.git.rahul.tanwar@linux.intel.com Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
145 lines
4.5 KiB
C
145 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(c) 2019 Intel Corporation.
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*/
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#ifndef __PINCTRL_EQUILIBRIUM_H
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#define __PINCTRL_EQUILIBRIUM_H
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/* PINPAD register offset */
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#define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */
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#define REG_PUEN 0x80 /* PULL UP Enable Register */
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#define REG_PDEN 0x84 /* PULL DOWN Enable Register */
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#define REG_SRC 0x88 /* Slew Rate Control Register */
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#define REG_DCC0 0x8C /* Drive Current Control Register 0 */
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#define REG_DCC1 0x90 /* Drive Current Control Register 1 */
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#define REG_OD 0x94 /* Open Drain Enable Register */
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#define REG_AVAIL 0x98 /* Pad Control Availability Register */
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#define DRV_CUR_PINS 16 /* Drive Current pin number per register */
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#define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */
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/* GPIO register offset */
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#define GPIO_OUT 0x0 /* Data Output Register */
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#define GPIO_IN 0x4 /* Data Input Register */
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#define GPIO_DIR 0x8 /* Direction Register */
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#define GPIO_EXINTCR0 0x18 /* External Interrupt Control Register 0 */
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#define GPIO_EXINTCR1 0x1C /* External Interrupt Control Register 1 */
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#define GPIO_IRNCR 0x20 /* IRN Capture Register */
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#define GPIO_IRNICR 0x24 /* IRN Interrupt Control Register */
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#define GPIO_IRNEN 0x28 /* IRN Interrupt Enable Register */
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#define GPIO_IRNCFG 0x2C /* IRN Interrupt Configuration Register */
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#define GPIO_IRNRNSET 0x30 /* IRN Interrupt Enable Set Register */
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#define GPIO_IRNENCLR 0x34 /* IRN Interrupt Enable Clear Register */
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#define GPIO_OUTSET 0x40 /* Output Set Register */
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#define GPIO_OUTCLR 0x44 /* Output Clear Register */
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#define GPIO_DIRSET 0x48 /* Direction Set Register */
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#define GPIO_DIRCLR 0x4C /* Direction Clear Register */
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/* parse given pin's driver current value */
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#define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3)
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#define GPIO_EDGE_TRIG 0
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#define GPIO_LEVEL_TRIG 1
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#define GPIO_SINGLE_EDGE 0
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#define GPIO_BOTH_EDGE 1
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#define GPIO_POSITIVE_TRIG 0
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#define GPIO_NEGATIVE_TRIG 1
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#define EQBR_GPIO_MODE 0
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typedef enum {
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OP_COUNT_NR_FUNCS,
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OP_ADD_FUNCS,
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OP_COUNT_NR_FUNC_GRPS,
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OP_ADD_FUNC_GRPS,
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OP_NONE,
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} funcs_util_ops;
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/**
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* struct gpio_irq_type: gpio irq configuration
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* @trig_type: level trigger or edge trigger
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* @edge_type: sigle edge or both edge
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* @logic_type: positive trigger or negative trigger
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*/
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struct gpio_irq_type {
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unsigned int trig_type;
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unsigned int edge_type;
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unsigned int logic_type;
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};
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/**
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* struct eqbr_pmx_func: represent a pin function.
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* @name: name of the pin function, used to lookup the function.
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* @groups: one or more names of pin groups that provide this function.
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* @nr_groups: number of groups included in @groups.
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*/
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struct eqbr_pmx_func {
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const char *name;
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const char **groups;
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unsigned int nr_groups;
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};
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/**
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* struct eqbr_pin_bank: represent a pin bank.
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* @membase: base address of the pin bank register.
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* @id: bank id, to idenify the unique bank.
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* @pin_base: starting pin number of the pin bank.
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* @nr_pins: number of the pins of the pin bank.
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* @aval_pinmap: available pin bitmap of the pin bank.
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*/
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struct eqbr_pin_bank {
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void __iomem *membase;
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unsigned int id;
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unsigned int pin_base;
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unsigned int nr_pins;
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u32 aval_pinmap;
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};
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/**
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* struct eqbr_gpio_ctrl: represent a gpio controller.
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* @node: device node of gpio controller.
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* @bank: pointer to corresponding pin bank.
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* @membase: base address of the gpio controller.
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* @chip: gpio chip.
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* @ic: irq chip.
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* @name: gpio chip name.
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* @virq: irq number of the gpio chip to parent's irq domain.
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* @lock: spin lock to protect gpio register write.
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*/
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struct eqbr_gpio_ctrl {
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struct device_node *node;
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struct eqbr_pin_bank *bank;
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void __iomem *membase;
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struct gpio_chip chip;
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struct irq_chip ic;
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const char *name;
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unsigned int virq;
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raw_spinlock_t lock; /* protect gpio register */
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};
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/**
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* struct eqbr_pinctrl_drv_data:
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* @dev: device instance representing the controller.
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* @pctl_desc: pin controller descriptor.
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* @pctl_dev: pin control class device
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* @membase: base address of pin controller
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* @pin_banks: list of pin banks of the driver.
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* @nr_banks: number of pin banks.
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* @gpio_ctrls: list of gpio controllers.
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* @nr_gpio_ctrls: number of gpio controllers.
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* @lock: protect pinctrl register write
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*/
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struct eqbr_pinctrl_drv_data {
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struct device *dev;
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struct pinctrl_desc pctl_desc;
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struct pinctrl_dev *pctl_dev;
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void __iomem *membase;
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struct eqbr_pin_bank *pin_banks;
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unsigned int nr_banks;
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struct eqbr_gpio_ctrl *gpio_ctrls;
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unsigned int nr_gpio_ctrls;
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raw_spinlock_t lock; /* protect pinpad register */
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};
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#endif /* __PINCTRL_EQUILIBRIUM_H */
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