367b8112fe
Move all header files for xtensa to arch/xtensa/include and platform and variant header files to the appropriate arch/xtensa/platforms/ and arch/xtensa/variants/ directories. Moving the files gets also rid of all uses of symlinks in the Makefile. This has been completed already for the majority of the architectures and xtensa is one out of six missing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Chris Zankel <chris@zankel.net>
178 lines
3.2 KiB
C
178 lines
3.2 KiB
C
/*
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* include/asm-xtensa/cacheasm.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Tensilica Inc.
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*/
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#include <asm/cache.h>
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#include <asm/asmmacro.h>
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#include <linux/stringify.h>
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/*
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* Define cache functions as macros here so that they can be used
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* by the kernel and boot loader. We should consider moving them to a
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* library that can be linked by both.
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*
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* Locking
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*
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* ___unlock_dcache_all
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* ___unlock_icache_all
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*
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* Flush and invaldating
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*
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* ___flush_invalidate_dcache_{all|range|page}
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* ___flush_dcache_{all|range|page}
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* ___invalidate_dcache_{all|range|page}
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* ___invalidate_icache_{all|range|page}
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*
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*/
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.macro __loop_cache_all ar at insn size line_width
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movi \ar, 0
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__loopi \ar, \at, \size, (4 << (\line_width))
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\insn \ar, 0 << (\line_width)
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\insn \ar, 1 << (\line_width)
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\insn \ar, 2 << (\line_width)
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\insn \ar, 3 << (\line_width)
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__endla \ar, \at, 4 << (\line_width)
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.endm
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.macro __loop_cache_range ar as at insn line_width
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extui \at, \ar, 0, \line_width
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add \as, \as, \at
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__loops \ar, \as, \at, \line_width
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\insn \ar, 0
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__endla \ar, \at, (1 << (\line_width))
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.endm
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.macro __loop_cache_page ar at insn line_width
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__loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
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\insn \ar, 0 << (\line_width)
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\insn \ar, 1 << (\line_width)
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\insn \ar, 2 << (\line_width)
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\insn \ar, 3 << (\line_width)
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__endla \ar, \at, 4 << (\line_width)
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.endm
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#if XCHAL_DCACHE_LINE_LOCKABLE
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.macro ___unlock_dcache_all ar at
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__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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.endm
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#endif
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#if XCHAL_ICACHE_LINE_LOCKABLE
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.macro ___unlock_icache_all ar at
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__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
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.endm
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#endif
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.macro ___flush_invalidate_dcache_all ar at
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__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___flush_dcache_all ar at
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__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___invalidate_dcache_all ar at
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__loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
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XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___invalidate_icache_all ar at
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__loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
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XCHAL_ICACHE_LINEWIDTH
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.endm
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.macro ___flush_invalidate_dcache_range ar as at
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__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___flush_dcache_range ar as at
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__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___invalidate_dcache_range ar as at
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__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___invalidate_icache_range ar as at
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__loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
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.endm
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.macro ___flush_invalidate_dcache_page ar as
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__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___flush_dcache_page ar as
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__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___invalidate_dcache_page ar as
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__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
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.endm
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.macro ___invalidate_icache_page ar as
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__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
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.endm
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