f49f49aa15
Bit pattern USP_RXFIFO_THD_INT is being bit-wise or'd twice; remove the redundant 2nd USP_RXFIFO_THD_INT Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Mark Brown <broonie@kernel.org>
294 lines
8.4 KiB
C
294 lines
8.4 KiB
C
/*
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* arch/arm/mach-prima2/include/mach/sirfsoc_usp.h
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#ifndef _SIRF_USP_H
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#define _SIRF_USP_H
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/* USP Registers */
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#define USP_MODE1 0x00
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#define USP_MODE2 0x04
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#define USP_TX_FRAME_CTRL 0x08
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#define USP_RX_FRAME_CTRL 0x0C
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#define USP_TX_RX_ENABLE 0x10
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#define USP_INT_ENABLE 0x14
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#define USP_INT_STATUS 0x18
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#define USP_PIN_IO_DATA 0x1C
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#define USP_RISC_DSP_MODE 0x20
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#define USP_AYSNC_PARAM_REG 0x24
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#define USP_IRDA_X_MODE_DIV 0x28
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#define USP_SM_CFG 0x2C
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#define USP_TX_DMA_IO_CTRL 0x100
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#define USP_TX_DMA_IO_LEN 0x104
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#define USP_TX_FIFO_CTRL 0x108
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#define USP_TX_FIFO_LEVEL_CHK 0x10C
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#define USP_TX_FIFO_OP 0x110
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#define USP_TX_FIFO_STATUS 0x114
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#define USP_TX_FIFO_DATA 0x118
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#define USP_RX_DMA_IO_CTRL 0x120
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#define USP_RX_DMA_IO_LEN 0x124
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#define USP_RX_FIFO_CTRL 0x128
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#define USP_RX_FIFO_LEVEL_CHK 0x12C
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#define USP_RX_FIFO_OP 0x130
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#define USP_RX_FIFO_STATUS 0x134
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#define USP_RX_FIFO_DATA 0x138
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/* USP MODE register-1 */
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#define USP_SYNC_MODE 0x00000001
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#define USP_CLOCK_MODE_SLAVE 0x00000002
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#define USP_LOOP_BACK_EN 0x00000004
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#define USP_HPSIR_EN 0x00000008
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#define USP_ENDIAN_CTRL_LSBF 0x00000010
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#define USP_EN 0x00000020
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#define USP_RXD_ACT_EDGE_FALLING 0x00000040
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#define USP_TXD_ACT_EDGE_FALLING 0x00000080
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#define USP_RFS_ACT_LEVEL_LOGIC1 0x00000100
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#define USP_TFS_ACT_LEVEL_LOGIC1 0x00000200
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#define USP_SCLK_IDLE_MODE_TOGGLE 0x00000400
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#define USP_SCLK_IDLE_LEVEL_LOGIC1 0x00000800
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#define USP_SCLK_PIN_MODE_IO 0x00001000
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#define USP_RFS_PIN_MODE_IO 0x00002000
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#define USP_TFS_PIN_MODE_IO 0x00004000
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#define USP_RXD_PIN_MODE_IO 0x00008000
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#define USP_TXD_PIN_MODE_IO 0x00010000
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#define USP_SCLK_IO_MODE_INPUT 0x00020000
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#define USP_RFS_IO_MODE_INPUT 0x00040000
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#define USP_TFS_IO_MODE_INPUT 0x00080000
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#define USP_RXD_IO_MODE_INPUT 0x00100000
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#define USP_TXD_IO_MODE_INPUT 0x00200000
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#define USP_IRDA_WIDTH_DIV_MASK 0x3FC00000
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#define USP_IRDA_WIDTH_DIV_OFFSET 0
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#define USP_IRDA_IDLE_LEVEL_HIGH 0x40000000
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#define USP_TX_UFLOW_REPEAT_ZERO 0x80000000
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#define USP_TX_ENDIAN_MODE 0x00000020
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#define USP_RX_ENDIAN_MODE 0x00000020
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/* USP Mode Register-2 */
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#define USP_RXD_DELAY_LEN_MASK 0x000000FF
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#define USP_RXD_DELAY_LEN_OFFSET 0
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#define USP_TXD_DELAY_LEN_MASK 0x0000FF00
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#define USP_TXD_DELAY_LEN_OFFSET 8
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#define USP_ENA_CTRL_MODE 0x00010000
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#define USP_FRAME_CTRL_MODE 0x00020000
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#define USP_TFS_SOURCE_MODE 0x00040000
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#define USP_TFS_MS_MODE 0x00080000
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#define USP_CLK_DIVISOR_MASK 0x7FE00000
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#define USP_CLK_DIVISOR_OFFSET 21
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#define USP_TFS_CLK_SLAVE_MODE (1<<20)
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#define USP_RFS_CLK_SLAVE_MODE (1<<19)
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#define USP_IRDA_DATA_WIDTH 0x80000000
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/* USP Transmit Frame Control Register */
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#define USP_TXC_DATA_LEN_MASK 0x000000FF
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#define USP_TXC_DATA_LEN_OFFSET 0
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#define USP_TXC_SYNC_LEN_MASK 0x0000FF00
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#define USP_TXC_SYNC_LEN_OFFSET 8
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#define USP_TXC_FRAME_LEN_MASK 0x00FF0000
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#define USP_TXC_FRAME_LEN_OFFSET 16
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#define USP_TXC_SHIFTER_LEN_MASK 0x1F000000
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#define USP_TXC_SHIFTER_LEN_OFFSET 24
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#define USP_TXC_SLAVE_CLK_SAMPLE 0x20000000
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#define USP_TXC_CLK_DIVISOR_MASK 0xC0000000
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#define USP_TXC_CLK_DIVISOR_OFFSET 30
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/* USP Receive Frame Control Register */
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#define USP_RXC_DATA_LEN_MASK 0x000000FF
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#define USP_RXC_DATA_LEN_OFFSET 0
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#define USP_RXC_FRAME_LEN_MASK 0x0000FF00
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#define USP_RXC_FRAME_LEN_OFFSET 8
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#define USP_RXC_SHIFTER_LEN_MASK 0x001F0000
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#define USP_RXC_SHIFTER_LEN_OFFSET 16
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#define USP_START_EDGE_MODE 0x00800000
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#define USP_I2S_SYNC_CHG 0x00200000
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#define USP_RXC_CLK_DIVISOR_MASK 0x0F000000
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#define USP_RXC_CLK_DIVISOR_OFFSET 24
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#define USP_SINGLE_SYNC_MODE 0x00400000
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/* Tx - RX Enable Register */
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#define USP_RX_ENA 0x00000001
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#define USP_TX_ENA 0x00000002
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/* USP Interrupt Enable and status Register */
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#define USP_RX_DONE_INT 0x00000001
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#define USP_TX_DONE_INT 0x00000002
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#define USP_RX_OFLOW_INT 0x00000004
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#define USP_TX_UFLOW_INT 0x00000008
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#define USP_RX_IO_DMA_INT 0x00000010
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#define USP_TX_IO_DMA_INT 0x00000020
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#define USP_RXFIFO_FULL_INT 0x00000040
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#define USP_TXFIFO_EMPTY_INT 0x00000080
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#define USP_RXFIFO_THD_INT 0x00000100
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#define USP_TXFIFO_THD_INT 0x00000200
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#define USP_UART_FRM_ERR_INT 0x00000400
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#define USP_RX_TIMEOUT_INT 0x00000800
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#define USP_TX_ALLOUT_INT 0x00001000
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#define USP_RXD_BREAK_INT 0x00008000
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/* All possible TX interruots */
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#define USP_TX_INTERRUPT (USP_TX_DONE_INT|USP_TX_UFLOW_INT|\
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USP_TX_IO_DMA_INT|\
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USP_TXFIFO_EMPTY_INT|\
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USP_TXFIFO_THD_INT)
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/* All possible RX interruots */
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#define USP_RX_INTERRUPT (USP_RX_DONE_INT|USP_RX_OFLOW_INT|\
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USP_RX_IO_DMA_INT|\
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USP_RXFIFO_FULL_INT|\
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USP_RXFIFO_THD_INT|\
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USP_RX_TIMEOUT_INT)
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#define USP_INT_ALL 0x1FFF
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/* USP Pin I/O Data Register */
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#define USP_RFS_PIN_VALUE_MASK 0x00000001
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#define USP_TFS_PIN_VALUE_MASK 0x00000002
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#define USP_RXD_PIN_VALUE_MASK 0x00000004
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#define USP_TXD_PIN_VALUE_MASK 0x00000008
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#define USP_SCLK_PIN_VALUE_MASK 0x00000010
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/* USP RISC/DSP Mode Register */
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#define USP_RISC_DSP_SEL 0x00000001
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/* USP ASYNC PARAMETER Register*/
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#define USP_ASYNC_TIMEOUT_MASK 0x0000FFFF
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#define USP_ASYNC_TIMEOUT_OFFSET 0
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#define USP_ASYNC_TIMEOUT(x) (((x)&USP_ASYNC_TIMEOUT_MASK) \
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<<USP_ASYNC_TIMEOUT_OFFSET)
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#define USP_ASYNC_DIV2_MASK 0x003F0000
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#define USP_ASYNC_DIV2_OFFSET 16
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/* USP TX DMA I/O MODE Register */
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#define USP_TX_MODE_IO 0x00000001
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/* USP TX DMA I/O Length Register */
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#define USP_TX_DATA_LEN_MASK 0xFFFFFFFF
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#define USP_TX_DATA_LEN_OFFSET 0
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/* USP TX FIFO Control Register */
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#define USP_TX_FIFO_WIDTH_MASK 0x00000003
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#define USP_TX_FIFO_WIDTH_OFFSET 0
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#define USP_TX_FIFO_THD_MASK 0x000001FC
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#define USP_TX_FIFO_THD_OFFSET 2
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/* USP TX FIFO Level Check Register */
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#define USP_TX_FIFO_LEVEL_CHECK_MASK 0x1F
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#define USP_TX_FIFO_SC_OFFSET 0
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#define USP_TX_FIFO_LC_OFFSET 10
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#define USP_TX_FIFO_HC_OFFSET 20
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#define TX_FIFO_SC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
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<< USP_TX_FIFO_SC_OFFSET)
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#define TX_FIFO_LC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
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<< USP_TX_FIFO_LC_OFFSET)
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#define TX_FIFO_HC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
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<< USP_TX_FIFO_HC_OFFSET)
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/* USP TX FIFO Operation Register */
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#define USP_TX_FIFO_RESET 0x00000001
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#define USP_TX_FIFO_START 0x00000002
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/* USP TX FIFO Status Register */
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#define USP_TX_FIFO_LEVEL_MASK 0x0000007F
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#define USP_TX_FIFO_LEVEL_OFFSET 0
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#define USP_TX_FIFO_FULL 0x00000080
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#define USP_TX_FIFO_EMPTY 0x00000100
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/* USP TX FIFO Data Register */
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#define USP_TX_FIFO_DATA_MASK 0xFFFFFFFF
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#define USP_TX_FIFO_DATA_OFFSET 0
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/* USP RX DMA I/O MODE Register */
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#define USP_RX_MODE_IO 0x00000001
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#define USP_RX_DMA_FLUSH 0x00000004
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/* USP RX DMA I/O Length Register */
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#define USP_RX_DATA_LEN_MASK 0xFFFFFFFF
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#define USP_RX_DATA_LEN_OFFSET 0
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/* USP RX FIFO Control Register */
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#define USP_RX_FIFO_WIDTH_MASK 0x00000003
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#define USP_RX_FIFO_WIDTH_OFFSET 0
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#define USP_RX_FIFO_THD_MASK 0x000001FC
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#define USP_RX_FIFO_THD_OFFSET 2
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/* USP RX FIFO Level Check Register */
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#define USP_RX_FIFO_LEVEL_CHECK_MASK 0x1F
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#define USP_RX_FIFO_SC_OFFSET 0
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#define USP_RX_FIFO_LC_OFFSET 10
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#define USP_RX_FIFO_HC_OFFSET 20
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#define RX_FIFO_SC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
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<< USP_RX_FIFO_SC_OFFSET)
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#define RX_FIFO_LC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
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<< USP_RX_FIFO_LC_OFFSET)
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#define RX_FIFO_HC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
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<< USP_RX_FIFO_HC_OFFSET)
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/* USP RX FIFO Operation Register */
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#define USP_RX_FIFO_RESET 0x00000001
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#define USP_RX_FIFO_START 0x00000002
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/* USP RX FIFO Status Register */
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#define USP_RX_FIFO_LEVEL_MASK 0x0000007F
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#define USP_RX_FIFO_LEVEL_OFFSET 0
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#define USP_RX_FIFO_FULL 0x00000080
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#define USP_RX_FIFO_EMPTY 0x00000100
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/* USP RX FIFO Data Register */
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#define USP_RX_FIFO_DATA_MASK 0xFFFFFFFF
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#define USP_RX_FIFO_DATA_OFFSET 0
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/*
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* When rx thd irq occur, sender just disable tx empty irq,
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* Remaining data in tx fifo wil also be sent out.
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*/
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#define USP_FIFO_SIZE 128
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#define USP_TX_FIFO_THRESHOLD (USP_FIFO_SIZE/2)
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#define USP_RX_FIFO_THRESHOLD (USP_FIFO_SIZE/2)
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/* FIFO_WIDTH for the USP_TX_FIFO_CTRL and USP_RX_FIFO_CTRL registers */
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#define USP_FIFO_WIDTH_BYTE 0x00
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#define USP_FIFO_WIDTH_WORD 0x01
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#define USP_FIFO_WIDTH_DWORD 0x02
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#define USP_ASYNC_DIV2 16
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#define USP_PLUGOUT_RETRY_CNT 2
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#define USP_TX_RX_FIFO_WIDTH_DWORD 2
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#define SIRF_USP_DIV_MCLK 0
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#define SIRF_USP_I2S_TFS_SYNC 0
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#define SIRF_USP_I2S_RFS_SYNC 1
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#endif
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