d06d5777b2
Add s_io_pin_config core subdev op for the CX2388[578] AV cores. This is complete for IR_RX, IR_TX, GPIOs 16,19-23, and IRQ_N. It likely needs work for the I2S signal direction. Signed-off-by: Andy Walls <awalls@md.metrocast.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
176 lines
4.8 KiB
C
176 lines
4.8 KiB
C
/*
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cx25840.h - definition for cx25840/1/2/3 inputs
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Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _CX25840_H_
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#define _CX25840_H_
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/* Note that the cx25840 driver requires that the bridge driver calls the
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v4l2_subdev's init operation in order to load the driver's firmware.
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Without this the audio standard detection will fail and you will
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only get mono.
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Since loading the firmware is often problematic when the driver is
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compiled into the kernel I recommend postponing calling this function
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until the first open of the video device. Another reason for
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postponing it is that loading this firmware takes a long time (seconds)
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due to the slow i2c bus speed. So it will speed up the boot process if
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you can avoid loading the fw as long as the video device isn't used. */
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enum cx25840_video_input {
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/* Composite video inputs In1-In8 */
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CX25840_COMPOSITE1 = 1,
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CX25840_COMPOSITE2,
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CX25840_COMPOSITE3,
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CX25840_COMPOSITE4,
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CX25840_COMPOSITE5,
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CX25840_COMPOSITE6,
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CX25840_COMPOSITE7,
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CX25840_COMPOSITE8,
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/* S-Video inputs consist of one luma input (In1-In8) ORed with one
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chroma input (In5-In8) */
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CX25840_SVIDEO_LUMA1 = 0x10,
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CX25840_SVIDEO_LUMA2 = 0x20,
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CX25840_SVIDEO_LUMA3 = 0x30,
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CX25840_SVIDEO_LUMA4 = 0x40,
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CX25840_SVIDEO_LUMA5 = 0x50,
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CX25840_SVIDEO_LUMA6 = 0x60,
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CX25840_SVIDEO_LUMA7 = 0x70,
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CX25840_SVIDEO_LUMA8 = 0x80,
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CX25840_SVIDEO_CHROMA4 = 0x400,
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CX25840_SVIDEO_CHROMA5 = 0x500,
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CX25840_SVIDEO_CHROMA6 = 0x600,
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CX25840_SVIDEO_CHROMA7 = 0x700,
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CX25840_SVIDEO_CHROMA8 = 0x800,
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/* S-Video aliases for common luma/chroma combinations */
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CX25840_SVIDEO1 = 0x510,
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CX25840_SVIDEO2 = 0x620,
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CX25840_SVIDEO3 = 0x730,
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CX25840_SVIDEO4 = 0x840,
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/* Allow frames to specify specific input configurations */
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CX25840_VIN1_CH1 = 0x80000000,
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CX25840_VIN2_CH1 = 0x80000001,
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CX25840_VIN3_CH1 = 0x80000002,
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CX25840_VIN4_CH1 = 0x80000003,
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CX25840_VIN5_CH1 = 0x80000004,
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CX25840_VIN6_CH1 = 0x80000005,
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CX25840_VIN7_CH1 = 0x80000006,
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CX25840_VIN8_CH1 = 0x80000007,
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CX25840_VIN4_CH2 = 0x80000000,
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CX25840_VIN5_CH2 = 0x80000010,
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CX25840_VIN6_CH2 = 0x80000020,
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CX25840_NONE_CH2 = 0x80000030,
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CX25840_VIN7_CH3 = 0x80000000,
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CX25840_VIN8_CH3 = 0x80000040,
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CX25840_NONE0_CH3 = 0x80000080,
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CX25840_NONE1_CH3 = 0x800000c0,
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CX25840_SVIDEO_ON = 0x80000100,
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CX25840_COMPONENT_ON = 0x80000200,
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};
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enum cx25840_audio_input {
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/* Audio inputs: serial or In4-In8 */
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CX25840_AUDIO_SERIAL,
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CX25840_AUDIO4 = 4,
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CX25840_AUDIO5,
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CX25840_AUDIO6,
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CX25840_AUDIO7,
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CX25840_AUDIO8,
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};
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enum cx25840_io_pin {
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CX25840_PIN_DVALID_PRGM0 = 0,
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CX25840_PIN_FIELD_PRGM1,
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CX25840_PIN_HRESET_PRGM2,
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CX25840_PIN_VRESET_HCTL_PRGM3,
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CX25840_PIN_IRQ_N_PRGM4,
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CX25840_PIN_IR_TX_PRGM6,
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CX25840_PIN_IR_RX_PRGM5,
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CX25840_PIN_GPIO0_PRGM8,
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CX25840_PIN_GPIO1_PRGM9,
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CX25840_PIN_SA_SDIN, /* Alternate GP Input only */
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CX25840_PIN_SA_SDOUT, /* Alternate GP Input only */
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CX25840_PIN_PLL_CLK_PRGM7,
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CX25840_PIN_CHIP_SEL_VIPCLK, /* Output only */
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};
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enum cx25840_io_pad {
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/* Output pads */
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CX25840_PAD_DEFAULT = 0,
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CX25840_PAD_ACTIVE,
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CX25840_PAD_VACTIVE,
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CX25840_PAD_CBFLAG,
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CX25840_PAD_VID_DATA_EXT0,
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CX25840_PAD_VID_DATA_EXT1,
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CX25840_PAD_GPO0,
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CX25840_PAD_GPO1,
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CX25840_PAD_GPO2,
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CX25840_PAD_GPO3,
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CX25840_PAD_IRQ_N,
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CX25840_PAD_AC_SYNC,
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CX25840_PAD_AC_SDOUT,
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CX25840_PAD_PLL_CLK,
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CX25840_PAD_VRESET,
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CX25840_PAD_RESERVED,
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/* Pads for PLL_CLK output only */
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CX25840_PAD_XTI_X5_DLL,
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CX25840_PAD_AUX_PLL,
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CX25840_PAD_VID_PLL,
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CX25840_PAD_XTI,
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/* Input Pads */
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CX25840_PAD_GPI0,
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CX25840_PAD_GPI1,
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CX25840_PAD_GPI2,
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CX25840_PAD_GPI3,
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};
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enum cx25840_io_pin_strength {
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CX25840_PIN_DRIVE_MEDIUM = 0,
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CX25840_PIN_DRIVE_SLOW,
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CX25840_PIN_DRIVE_FAST,
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};
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enum cx23885_io_pin {
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CX23885_PIN_IR_RX_GPIO19,
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CX23885_PIN_IR_TX_GPIO20,
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CX23885_PIN_I2S_SDAT_GPIO21,
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CX23885_PIN_I2S_WCLK_GPIO22,
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CX23885_PIN_I2S_BCLK_GPIO23,
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CX23885_PIN_IRQ_N_GPIO16,
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};
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enum cx23885_io_pad {
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CX23885_PAD_IR_RX,
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CX23885_PAD_GPIO19,
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CX23885_PAD_IR_TX,
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CX23885_PAD_GPIO20,
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CX23885_PAD_I2S_SDAT,
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CX23885_PAD_GPIO21,
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CX23885_PAD_I2S_WCLK,
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CX23885_PAD_GPIO22,
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CX23885_PAD_I2S_BCLK,
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CX23885_PAD_GPIO23,
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CX23885_PAD_IRQ_N,
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CX23885_PAD_GPIO16,
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};
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#endif
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