Andy Shevchenko d2f78e95e4 dmaengine: dw: enable clock before access ... hclk signal is a bus clock. So, it means we have to have it enabled during access to the DMA controller. This patch makes sure that we enable clock before access to the device, though it currently works on Intel hardware. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>		2014-05-22 15:37:24 +05:30
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core.c	dmaengine: dw: enable clock before access	2014-05-22 15:37:24 +05:30
internal.h	dma: dw: split driver to library part and platform code	2013-07-05 11:40:44 +05:30
Kconfig	Remove GENERIC_HARDIRQ config option	2013-09-13 15:09:52 +02:00
Makefile	dma: dw: add PCI part of the driver	2013-07-05 11:40:45 +05:30
pci.c	dma: dw: Add suspend and resume handling for PCI mode DW_DMAC.	2014-03-26 11:52:03 +05:30
platform.c	DMA-API: dma: dw_dmac.c: convert to use dma_coerce_mask_and_coherent()	2013-10-31 14:48:51 +00:00
regs.h	dma: dw: allocate memory in two stages in probe	2014-03-26 11:44:27 +05:30