ced0f005c7
- Move EXPORT_SYMBOL lines of delay loop functions from arch/m32r/kernel/m32r_ksyms.c to arch/m32r/lib/delay.c. - Export __ndelay. Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
/*
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* linux/arch/m32r/lib/delay.c
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*
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* Copyright (c) 2002 Hitoshi Yamamoto, Hirokazu Takata
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* Copyright (c) 2004 Hirokazu Takata
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*/
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#include <linux/param.h>
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#include <linux/module.h>
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#ifdef CONFIG_SMP
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#include <linux/sched.h>
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#include <asm/current.h>
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#include <asm/smp.h>
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#endif /* CONFIG_SMP */
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#include <asm/processor.h>
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void __delay(unsigned long loops)
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{
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#ifdef CONFIG_ISA_DUAL_ISSUE
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__asm__ __volatile__ (
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"beqz %0, 2f \n\t"
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"addi %0, #-1 \n\t"
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" .fillinsn \n\t"
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"1: \n\t"
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"cmpz %0 || addi %0, #-1 \n\t"
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"bc 2f || cmpz %0 \n\t"
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"bc 2f || addi %0, #-1 \n\t"
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"cmpz %0 || addi %0, #-1 \n\t"
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"bc 2f || cmpz %0 \n\t"
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"bnc 1b || addi %0, #-1 \n\t"
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" .fillinsn \n\t"
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"2: \n\t"
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: "+r" (loops)
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: "r" (0)
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: "cbit"
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);
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#else
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__asm__ __volatile__ (
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"beqz %0, 2f \n\t"
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" .fillinsn \n\t"
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"1: \n\t"
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"addi %0, #-1 \n\t"
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"blez %0, 2f \n\t"
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"addi %0, #-1 \n\t"
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"blez %0, 2f \n\t"
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"addi %0, #-1 \n\t"
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"blez %0, 2f \n\t"
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"addi %0, #-1 \n\t"
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"bgtz %0, 1b \n\t"
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" .fillinsn \n\t"
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"2: \n\t"
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: "+r" (loops)
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: "r" (0)
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);
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#endif
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}
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void __const_udelay(unsigned long xloops)
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{
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#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
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/*
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* loops [1] = (xloops >> 32) [sec] * loops_per_jiffy [1/jiffy]
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* * HZ [jiffy/sec]
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* = (xloops >> 32) [sec] * (loops_per_jiffy * HZ) [1/sec]
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* = (((xloops * loops_per_jiffy) >> 32) * HZ) [1]
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*
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* NOTE:
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* - '[]' depicts variable's dimension in the above equation.
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* - "rac" instruction rounds the accumulator in word size.
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*/
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__asm__ __volatile__ (
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"srli %0, #1 \n\t"
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"mulwhi %0, %1 ; a0 \n\t"
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"mulwu1 %0, %1 ; a1 \n\t"
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"sadd ; a0 += (a1 >> 16) \n\t"
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"rac a0, a0, #1 \n\t"
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"mvfacmi %0, a0 \n\t"
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: "+r" (xloops)
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: "r" (current_cpu_data.loops_per_jiffy)
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: "a0", "a1"
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);
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#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
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/*
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* u64 ull;
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* ull = (u64)xloops * (u64)current_cpu_data.loops_per_jiffy;
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* xloops = (ull >> 32);
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*/
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__asm__ __volatile__ (
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"and3 r4, %0, #0xffff \n\t"
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"and3 r5, %1, #0xffff \n\t"
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"mul r4, r5 \n\t"
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"srl3 r6, %0, #16 \n\t"
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"srli r4, #16 \n\t"
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"mul r5, r6 \n\t"
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"add r4, r5 \n\t"
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"and3 r5, %0, #0xffff \n\t"
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"srl3 r6, %1, #16 \n\t"
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"mul r5, r6 \n\t"
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"add r4, r5 \n\t"
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"srl3 r5, %0, #16 \n\t"
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"srli r4, #16 \n\t"
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"mul r5, r6 \n\t"
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"add r4, r5 \n\t"
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"mv %0, r4 \n\t"
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: "+r" (xloops)
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: "r" (current_cpu_data.loops_per_jiffy)
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: "r4", "r5", "r6"
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);
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#else
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#error unknown isa configuration
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#endif
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__delay(xloops * HZ);
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}
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void __udelay(unsigned long usecs)
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{
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__const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
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}
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void __ndelay(unsigned long nsecs)
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{
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__const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
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}
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EXPORT_SYMBOL(__delay);
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EXPORT_SYMBOL(__const_udelay);
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EXPORT_SYMBOL(__udelay);
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EXPORT_SYMBOL(__ndelay);
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