9c76b38476
Use the functionality just introduced in the previous patch: mark the lock prefixes in cmpxchg64 alternatives for UP removal. Changes in v2: - Naming change Signed-off-by: Luca Barbieri <luca@luca-barbieri.com> LKML-Reference: <1267005265-27958-3-git-send-email-luca@luca-barbieri.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
304 lines
8.4 KiB
C
304 lines
8.4 KiB
C
#ifndef _ASM_X86_CMPXCHG_32_H
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#define _ASM_X86_CMPXCHG_32_H
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#include <linux/bitops.h> /* for LOCK_PREFIX */
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/*
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* Note: if you use set64_bit(), __cmpxchg64(), or their variants, you
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* you need to test for the feature in boot_cpu_data.
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*/
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extern void __xchg_wrong_size(void);
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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struct __xchg_dummy {
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unsigned long a[100];
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};
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#define __xg(x) ((struct __xchg_dummy *)(x))
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#define __xchg(x, ptr, size) \
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({ \
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__typeof(*(ptr)) __x = (x); \
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switch (size) { \
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case 1: \
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asm volatile("xchgb %b0,%1" \
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: "=q" (__x) \
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: "m" (*__xg(ptr)), "0" (__x) \
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: "memory"); \
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break; \
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case 2: \
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asm volatile("xchgw %w0,%1" \
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: "=r" (__x) \
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: "m" (*__xg(ptr)), "0" (__x) \
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: "memory"); \
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break; \
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case 4: \
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asm volatile("xchgl %0,%1" \
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: "=r" (__x) \
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: "m" (*__xg(ptr)), "0" (__x) \
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: "memory"); \
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break; \
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default: \
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__xchg_wrong_size(); \
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} \
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__x; \
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})
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#define xchg(ptr, v) \
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__xchg((v), (ptr), sizeof(*ptr))
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/*
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* The semantics of XCHGCMP8B are a bit strange, this is why
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* there is a loop and the loading of %%eax and %%edx has to
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* be inside. This inlines well in most cases, the cached
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* cost is around ~38 cycles. (in the future we might want
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* to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
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* might have an implicit FPU-save as a cost, so it's not
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* clear which path to go.)
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*
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* cmpxchg8b must be used with the lock prefix here to allow
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* the instruction to be executed atomically, see page 3-102
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* of the instruction set reference 24319102.pdf. We need
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* the reader side to see the coherent 64bit value.
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*/
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static inline void __set_64bit(unsigned long long *ptr,
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unsigned int low, unsigned int high)
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{
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asm volatile("\n1:\t"
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"movl (%0), %%eax\n\t"
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"movl 4(%0), %%edx\n\t"
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LOCK_PREFIX "cmpxchg8b (%0)\n\t"
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"jnz 1b"
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: /* no outputs */
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: "D"(ptr),
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"b"(low),
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"c"(high)
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: "ax", "dx", "memory");
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}
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static inline void __set_64bit_constant(unsigned long long *ptr,
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unsigned long long value)
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{
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__set_64bit(ptr, (unsigned int)value, (unsigned int)(value >> 32));
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}
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#define ll_low(x) *(((unsigned int *)&(x)) + 0)
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#define ll_high(x) *(((unsigned int *)&(x)) + 1)
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static inline void __set_64bit_var(unsigned long long *ptr,
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unsigned long long value)
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{
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__set_64bit(ptr, ll_low(value), ll_high(value));
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}
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#define set_64bit(ptr, value) \
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(__builtin_constant_p((value)) \
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? __set_64bit_constant((ptr), (value)) \
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: __set_64bit_var((ptr), (value)))
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#define _set_64bit(ptr, value) \
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(__builtin_constant_p(value) \
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? __set_64bit(ptr, (unsigned int)(value), \
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(unsigned int)((value) >> 32)) \
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: __set_64bit(ptr, ll_low((value)), ll_high((value))))
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extern void __cmpxchg_wrong_size(void);
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __raw_cmpxchg(ptr, old, new, size, lock) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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switch (size) { \
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case 1: \
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asm volatile(lock "cmpxchgb %b1,%2" \
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: "=a"(__ret) \
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: "q"(__new), "m"(*__xg(ptr)), "0"(__old) \
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: "memory"); \
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break; \
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case 2: \
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asm volatile(lock "cmpxchgw %w1,%2" \
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: "=a"(__ret) \
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: "r"(__new), "m"(*__xg(ptr)), "0"(__old) \
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: "memory"); \
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break; \
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case 4: \
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asm volatile(lock "cmpxchgl %1,%2" \
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: "=a"(__ret) \
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: "r"(__new), "m"(*__xg(ptr)), "0"(__old) \
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: "memory"); \
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break; \
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default: \
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__cmpxchg_wrong_size(); \
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} \
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__ret; \
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})
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#define __cmpxchg(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
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#define __sync_cmpxchg(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), "lock; ")
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#define __cmpxchg_local(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), "")
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#ifdef CONFIG_X86_CMPXCHG
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#define __HAVE_ARCH_CMPXCHG 1
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#define cmpxchg(ptr, old, new) \
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__cmpxchg((ptr), (old), (new), sizeof(*ptr))
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#define sync_cmpxchg(ptr, old, new) \
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__sync_cmpxchg((ptr), (old), (new), sizeof(*ptr))
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#define cmpxchg_local(ptr, old, new) \
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__cmpxchg_local((ptr), (old), (new), sizeof(*ptr))
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#endif
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#ifdef CONFIG_X86_CMPXCHG64
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#define cmpxchg64(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)))
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#define cmpxchg64_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)))
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#endif
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static inline unsigned long long __cmpxchg64(volatile void *ptr,
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unsigned long long old,
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unsigned long long new)
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{
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unsigned long long prev;
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asm volatile(LOCK_PREFIX "cmpxchg8b %3"
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: "=A"(prev)
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: "b"((unsigned long)new),
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"c"((unsigned long)(new >> 32)),
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"m"(*__xg(ptr)),
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"0"(old)
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: "memory");
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return prev;
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}
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static inline unsigned long long __cmpxchg64_local(volatile void *ptr,
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unsigned long long old,
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unsigned long long new)
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{
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unsigned long long prev;
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asm volatile("cmpxchg8b %3"
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: "=A"(prev)
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: "b"((unsigned long)new),
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"c"((unsigned long)(new >> 32)),
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"m"(*__xg(ptr)),
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"0"(old)
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: "memory");
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return prev;
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}
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#ifndef CONFIG_X86_CMPXCHG
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/*
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* Building a kernel capable running on 80386. It may be necessary to
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* simulate the cmpxchg on the 80386 CPU. For that purpose we define
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* a function for each of the sizes we support.
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*/
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extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
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extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
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extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
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static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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return cmpxchg_386_u8(ptr, old, new);
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case 2:
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return cmpxchg_386_u16(ptr, old, new);
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case 4:
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return cmpxchg_386_u32(ptr, old, new);
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}
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return old;
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}
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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if (likely(boot_cpu_data.x86 > 3)) \
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__ret = (__typeof__(*(ptr)))__cmpxchg((ptr), \
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(unsigned long)(o), (unsigned long)(n), \
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sizeof(*(ptr))); \
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else \
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__ret = (__typeof__(*(ptr)))cmpxchg_386((ptr), \
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(unsigned long)(o), (unsigned long)(n), \
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sizeof(*(ptr))); \
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__ret; \
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})
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#define cmpxchg_local(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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if (likely(boot_cpu_data.x86 > 3)) \
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__ret = (__typeof__(*(ptr)))__cmpxchg_local((ptr), \
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(unsigned long)(o), (unsigned long)(n), \
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sizeof(*(ptr))); \
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else \
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__ret = (__typeof__(*(ptr)))cmpxchg_386((ptr), \
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(unsigned long)(o), (unsigned long)(n), \
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sizeof(*(ptr))); \
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__ret; \
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})
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#endif
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#ifndef CONFIG_X86_CMPXCHG64
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/*
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* Building a kernel capable running on 80386 and 80486. It may be necessary
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* to simulate the cmpxchg8b on the 80386 and 80486 CPU.
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*/
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extern unsigned long long cmpxchg_486_u64(volatile void *, u64, u64);
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#define cmpxchg64(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__typeof__(*(ptr)) __old = (o); \
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__typeof__(*(ptr)) __new = (n); \
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alternative_io(LOCK_PREFIX_HERE \
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"call cmpxchg8b_emu", \
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"lock; cmpxchg8b (%%esi)" , \
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X86_FEATURE_CX8, \
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"=A" (__ret), \
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"S" ((ptr)), "0" (__old), \
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"b" ((unsigned int)__new), \
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"c" ((unsigned int)(__new>>32)) \
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: "memory"); \
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__ret; })
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#define cmpxchg64_local(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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if (likely(boot_cpu_data.x86 > 4)) \
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__ret = (__typeof__(*(ptr)))__cmpxchg64_local((ptr), \
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(unsigned long long)(o), \
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(unsigned long long)(n)); \
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else \
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__ret = (__typeof__(*(ptr)))cmpxchg_486_u64((ptr), \
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(unsigned long long)(o), \
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(unsigned long long)(n)); \
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__ret; \
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})
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#endif
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#endif /* _ASM_X86_CMPXCHG_32_H */
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