cbaa118ecf
Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
99 lines
2.4 KiB
C
99 lines
2.4 KiB
C
/*
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* arch/sh/mm/tlb-sh4.c
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*
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* SH-4 specific TLB operations
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2002 - 2007 Paul Mundt
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*
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* Released under the terms of the GNU GPL v2.0.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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void update_mmu_cache(struct vm_area_struct * vma,
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unsigned long address, pte_t pte)
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{
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unsigned long flags;
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unsigned long pteval;
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unsigned long vpn;
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/* Ptrace may call this routine. */
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if (vma && current->active_mm != vma->vm_mm)
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return;
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#ifndef CONFIG_CACHE_OFF
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{
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unsigned long pfn = pte_pfn(pte);
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if (pfn_valid(pfn)) {
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struct page *page = pfn_to_page(pfn);
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if (!test_bit(PG_mapped, &page->flags)) {
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unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
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__flush_wback_region((void *)P1SEGADDR(phys),
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PAGE_SIZE);
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__set_bit(PG_mapped, &page->flags);
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}
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}
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}
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#endif
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local_irq_save(flags);
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/* Set PTEH register */
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vpn = (address & MMU_VPN_MASK) | get_asid();
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ctrl_outl(vpn, MMU_PTEH);
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pteval = pte.pte_low;
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/* Set PTEA register */
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#ifdef CONFIG_X2TLB
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/*
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* For the extended mode TLB this is trivial, only the ESZ and
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* EPR bits need to be written out to PTEA, with the remainder of
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* the protection bits (with the exception of the compat-mode SZ
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* and PR bits, which are cleared) being written out in PTEL.
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*/
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ctrl_outl(pte.pte_high, MMU_PTEA);
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#else
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if (cpu_data->flags & CPU_HAS_PTEA)
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/* TODO: make this look less hacky */
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ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
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#endif
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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#ifdef CONFIG_CACHE_WRITETHROUGH
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pteval |= _PAGE_WT;
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#endif
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/* conveniently, we want all the software flags to be 0 anyway */
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ctrl_outl(pteval, MMU_PTEL);
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/* Load the TLB */
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asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
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local_irq_restore(flags);
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}
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void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
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unsigned long page)
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{
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unsigned long addr, data;
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/*
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* NOTE: PTEH.ASID should be set to this MM
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* _AND_ we need to write ASID to the array.
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*
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* It would be simple if we didn't need to set PTEH.ASID...
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*/
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addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
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data = page | asid; /* VALID bit is off */
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jump_to_uncached();
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ctrl_outl(data, addr);
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back_to_cached();
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}
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