6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
305 lines
8.2 KiB
C
305 lines
8.2 KiB
C
/*
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* linux/drivers/ide/pci/cs5535.c
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*
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* Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
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*
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* History:
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* 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
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* - Reworked tuneproc, set_drive, misc mods to prep for mainline
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* - Work was sponsored by CIS (M) Sdn Bhd.
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* Ported to Kernel 2.6.11 on June 26, 2005 by
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* Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
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* Alexander Kiausch <alex.kiausch@t-online.de>
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* Originally developed by AMD for 2.4/2.6
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*
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* Development of this chipset driver was funded
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* by the nice folks at National Semiconductor/AMD.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* Documentation:
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* CS5535 documentation available from AMD
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include "ide-timing.h"
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#define MSR_ATAC_BASE 0x51300000
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#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
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#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
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#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
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#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
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#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
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#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
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#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
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#define ATAC_RESET (MSR_ATAC_BASE+0x10)
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#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
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#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
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#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
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#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
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#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
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#define ATAC_BM0_CMD_PRIM 0x00
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#define ATAC_BM0_STS_PRIM 0x02
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#define ATAC_BM0_PRD 0x04
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#define CS5535_CABLE_DETECT 0x48
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/* Format I PIO settings. We seperate out cmd and data for safer timings */
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static unsigned int cs5535_pio_cmd_timings[5] =
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{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
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static unsigned int cs5535_pio_dta_timings[5] =
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{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
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static unsigned int cs5535_mwdma_timings[3] =
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{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
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static unsigned int cs5535_udma_timings[5] =
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{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
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/* Macros to check if the register is the reset value - reset value is an
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invalid timing and indicates the register has not been set previously */
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#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
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#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
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/****
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* cs5535_set_speed - Configure the chipset to the new speed
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* @drive: Drive to set up
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* @speed: desired speed
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*
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* cs5535_set_speed() configures the chipset to a new speed.
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*/
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static void cs5535_set_speed(ide_drive_t *drive, u8 speed)
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{
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u32 reg = 0, dummy;
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int unit = drive->select.b.unit;
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/* Set the PIO timings */
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if ((speed & XFER_MODE) == XFER_PIO) {
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u8 pioa;
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u8 piob;
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u8 cmd;
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pioa = speed - XFER_PIO_0;
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piob = ide_get_best_pio_mode(&(drive->hwif->drives[!unit]),
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255, 4, NULL);
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cmd = pioa < piob ? pioa : piob;
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/* Write the speed of the current drive */
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reg = (cs5535_pio_cmd_timings[cmd] << 16) |
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cs5535_pio_dta_timings[pioa];
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wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
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/* And if nessesary - change the speed of the other drive */
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rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
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if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
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cs5535_pio_cmd_timings[cmd]) {
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reg &= 0x0000FFFF;
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reg |= cs5535_pio_cmd_timings[cmd] << 16;
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wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
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}
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/* Set bit 31 of the DMA register for PIO format 1 timings */
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rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
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wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
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reg | 0x80000000UL, 0);
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} else {
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rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
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reg &= 0x80000000UL; /* Preserve the PIO format bit */
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if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_7)
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reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
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else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
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reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
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else
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return;
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wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
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}
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}
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static u8 cs5535_ratemask(ide_drive_t *drive)
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{
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/* eighty93 will return 1 if it's 80core and capable of
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exceeding udma2, 0 otherwise. we need ratemask to set
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the max speed and if we can > udma2 then we return 2
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which selects speed_max as udma4 which is the 5535's max
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speed, and 1 selects udma2 which is the max for 40c */
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if (!eighty_ninty_three(drive))
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return 1;
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return 2;
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}
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/****
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* cs5535_set_drive - Configure the drive to the new speed
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* @drive: Drive to set up
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* @speed: desired speed
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*
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* cs5535_set_drive() configures the drive and the chipset to a
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* new speed. It also can be called by upper layers.
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*/
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static int cs5535_set_drive(ide_drive_t *drive, u8 speed)
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{
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speed = ide_rate_filter(cs5535_ratemask(drive), speed);
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ide_config_drive_speed(drive, speed);
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cs5535_set_speed(drive, speed);
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return 0;
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}
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/****
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* cs5535_tuneproc - PIO setup
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* @drive: drive to set up
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* @pio: mode to use (255 for 'best possible')
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*
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* A callback from the upper layers for PIO-only tuning.
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*/
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static void cs5535_tuneproc(ide_drive_t *drive, u8 xferspeed)
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{
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u8 modes[] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3,
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XFER_PIO_4 };
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/* cs5535 max pio is pio 4, best_pio will check the blacklist.
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i think we don't need to rate_filter the incoming xferspeed
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since we know we're only going to choose pio */
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xferspeed = ide_get_best_pio_mode(drive, xferspeed, 4, NULL);
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ide_config_drive_speed(drive, modes[xferspeed]);
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cs5535_set_speed(drive, xferspeed);
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}
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static int cs5535_config_drive_for_dma(ide_drive_t *drive)
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{
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u8 speed;
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speed = ide_dma_speed(drive, cs5535_ratemask(drive));
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/* If no DMA speed was available then let dma_check hit pio */
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if (!speed) {
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return 0;
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}
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cs5535_set_drive(drive, speed);
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return ide_dma_enable(drive);
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}
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static int cs5535_dma_check(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct hd_driveid *id = drive->id;
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u8 speed;
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drive->init_speed = 0;
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if ((id->capability & 1) && drive->autodma) {
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if (ide_use_dma(drive)) {
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if (cs5535_config_drive_for_dma(drive))
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return hwif->ide_dma_on(drive);
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}
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goto fast_ata_pio;
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} else if ((id->capability & 8) || (id->field_valid & 2)) {
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fast_ata_pio:
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speed = ide_get_best_pio_mode(drive, 255, 4, NULL);
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cs5535_set_drive(drive, speed);
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return hwif->ide_dma_off_quietly(drive);
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}
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/* IORDY not supported */
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return 0;
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}
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static u8 __devinit cs5535_cable_detect(struct pci_dev *dev)
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{
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u8 bit;
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/* if a 80 wire cable was detected */
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pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
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return (bit & 1);
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}
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/****
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* init_hwif_cs5535 - Initialize one ide cannel
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* @hwif: Channel descriptor
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*
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* This gets invoked by the IDE driver once for each channel. It
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* performs channel-specific pre-initialization before drive probing.
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*
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*/
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static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
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{
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int i;
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hwif->autodma = 0;
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hwif->tuneproc = &cs5535_tuneproc;
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hwif->speedproc = &cs5535_set_drive;
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hwif->ide_dma_check = &cs5535_dma_check;
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hwif->atapi_dma = 1;
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hwif->ultra_mask = 0x1F;
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hwif->mwdma_mask = 0x07;
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hwif->udma_four = cs5535_cable_detect(hwif->pci_dev);
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if (!noautodma)
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hwif->autodma = 1;
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/* just setting autotune and not worrying about bios timings */
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for (i = 0; i < 2; i++) {
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hwif->drives[i].autotune = 1;
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hwif->drives[i].autodma = hwif->autodma;
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}
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}
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static ide_pci_device_t cs5535_chipset __devinitdata = {
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.name = "CS5535",
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.init_hwif = init_hwif_cs5535,
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.channels = 1,
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.autodma = AUTODMA,
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.bootable = ON_BOARD,
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};
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static int __devinit cs5535_init_one(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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return ide_setup_pci_device(dev, &cs5535_chipset);
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}
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static struct pci_device_id cs5535_pci_tbl[] =
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{
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{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_IDE, PCI_ANY_ID,
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PCI_ANY_ID, 0, 0, 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
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static struct pci_driver driver = {
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.name = "CS5535_IDE",
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.id_table = cs5535_pci_tbl,
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.probe = cs5535_init_one,
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};
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static int __init cs5535_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(cs5535_ide_init);
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MODULE_AUTHOR("AMD");
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MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
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MODULE_LICENSE("GPL");
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