1354b38b3d
Recent firmware will store PCI MIO information also when enabling MIO
instructions via set PCI function. We do not use this information but
currently calling enable MIO will fail because of insufficient response
block length. Fix this by putting a struct mio_info at the end of the
affected response block struct.
Fixes: 71ba41c9b1
("s390/pci: provide support for MIO instructions")
Signed-off-by: Sebastian Ott <sebott@linux.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
658 lines
14 KiB
C
658 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright IBM Corp. 2012
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*
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* Author(s):
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* Jan Glauber <jang@linux.vnet.ibm.com>
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*/
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#define KMSG_COMPONENT "zpci"
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#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
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#include <linux/compat.h>
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#include <linux/kernel.h>
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#include <linux/miscdevice.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/uaccess.h>
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#include <asm/pci_debug.h>
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#include <asm/pci_clp.h>
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#include <asm/clp.h>
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#include <uapi/asm/clp.h>
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bool zpci_unique_uid;
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static void update_uid_checking(bool new)
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{
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if (zpci_unique_uid != new)
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zpci_dbg(1, "uid checking:%d\n", new);
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zpci_unique_uid = new;
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}
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static inline void zpci_err_clp(unsigned int rsp, int rc)
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{
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struct {
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unsigned int rsp;
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int rc;
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} __packed data = {rsp, rc};
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zpci_err_hex(&data, sizeof(data));
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}
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/*
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* Call Logical Processor with c=1, lps=0 and command 1
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* to get the bit mask of installed logical processors
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*/
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static inline int clp_get_ilp(unsigned long *ilp)
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{
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unsigned long mask;
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int cc = 3;
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asm volatile (
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" .insn rrf,0xb9a00000,%[mask],%[cmd],8,0\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [mask] "=d" (mask) : [cmd] "a" (1)
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: "cc");
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*ilp = mask;
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return cc;
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}
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/*
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* Call Logical Processor with c=0, the give constant lps and an lpcb request.
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*/
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static inline int clp_req(void *data, unsigned int lps)
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{
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struct { u8 _[CLP_BLK_SIZE]; } *req = data;
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u64 ignored;
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int cc = 3;
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asm volatile (
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" .insn rrf,0xb9a00000,%[ign],%[req],0,%[lps]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [ign] "=d" (ignored), "+m" (*req)
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: [req] "a" (req), [lps] "i" (lps)
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: "cc");
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return cc;
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}
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static void *clp_alloc_block(gfp_t gfp_mask)
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{
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return (void *) __get_free_pages(gfp_mask, get_order(CLP_BLK_SIZE));
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}
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static void clp_free_block(void *ptr)
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{
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free_pages((unsigned long) ptr, get_order(CLP_BLK_SIZE));
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}
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static void clp_store_query_pci_fngrp(struct zpci_dev *zdev,
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struct clp_rsp_query_pci_grp *response)
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{
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zdev->tlb_refresh = response->refresh;
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zdev->dma_mask = response->dasm;
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zdev->msi_addr = response->msia;
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zdev->max_msi = response->noi;
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zdev->fmb_update = response->mui;
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switch (response->version) {
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case 1:
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zdev->max_bus_speed = PCIE_SPEED_5_0GT;
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break;
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default:
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zdev->max_bus_speed = PCI_SPEED_UNKNOWN;
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break;
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}
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}
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static int clp_query_pci_fngrp(struct zpci_dev *zdev, u8 pfgid)
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{
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struct clp_req_rsp_query_pci_grp *rrb;
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int rc;
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rrb = clp_alloc_block(GFP_KERNEL);
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if (!rrb)
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return -ENOMEM;
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memset(rrb, 0, sizeof(*rrb));
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rrb->request.hdr.len = sizeof(rrb->request);
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rrb->request.hdr.cmd = CLP_QUERY_PCI_FNGRP;
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rrb->response.hdr.len = sizeof(rrb->response);
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rrb->request.pfgid = pfgid;
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rc = clp_req(rrb, CLP_LPS_PCI);
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if (!rc && rrb->response.hdr.rsp == CLP_RC_OK)
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clp_store_query_pci_fngrp(zdev, &rrb->response);
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else {
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zpci_err("Q PCI FGRP:\n");
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zpci_err_clp(rrb->response.hdr.rsp, rc);
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rc = -EIO;
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}
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clp_free_block(rrb);
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return rc;
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}
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static int clp_store_query_pci_fn(struct zpci_dev *zdev,
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struct clp_rsp_query_pci *response)
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{
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int i;
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for (i = 0; i < PCI_BAR_COUNT; i++) {
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zdev->bars[i].val = le32_to_cpu(response->bar[i]);
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zdev->bars[i].size = response->bar_size[i];
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}
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zdev->start_dma = response->sdma;
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zdev->end_dma = response->edma;
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zdev->pchid = response->pchid;
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zdev->pfgid = response->pfgid;
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zdev->pft = response->pft;
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zdev->vfn = response->vfn;
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zdev->uid = response->uid;
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zdev->fmb_length = sizeof(u32) * response->fmb_len;
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memcpy(zdev->pfip, response->pfip, sizeof(zdev->pfip));
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if (response->util_str_avail) {
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memcpy(zdev->util_str, response->util_str,
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sizeof(zdev->util_str));
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}
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zdev->mio_capable = response->mio_addr_avail;
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for (i = 0; i < PCI_BAR_COUNT; i++) {
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if (!(response->mio.valid & (1 << (PCI_BAR_COUNT - i - 1))))
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continue;
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zdev->bars[i].mio_wb = (void __iomem *) response->mio.addr[i].wb;
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zdev->bars[i].mio_wt = (void __iomem *) response->mio.addr[i].wt;
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}
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return 0;
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}
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static int clp_query_pci_fn(struct zpci_dev *zdev, u32 fh)
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{
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struct clp_req_rsp_query_pci *rrb;
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int rc;
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rrb = clp_alloc_block(GFP_KERNEL);
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if (!rrb)
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return -ENOMEM;
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memset(rrb, 0, sizeof(*rrb));
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rrb->request.hdr.len = sizeof(rrb->request);
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rrb->request.hdr.cmd = CLP_QUERY_PCI_FN;
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rrb->response.hdr.len = sizeof(rrb->response);
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rrb->request.fh = fh;
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rc = clp_req(rrb, CLP_LPS_PCI);
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if (!rc && rrb->response.hdr.rsp == CLP_RC_OK) {
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rc = clp_store_query_pci_fn(zdev, &rrb->response);
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if (rc)
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goto out;
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rc = clp_query_pci_fngrp(zdev, rrb->response.pfgid);
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} else {
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zpci_err("Q PCI FN:\n");
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zpci_err_clp(rrb->response.hdr.rsp, rc);
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rc = -EIO;
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}
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out:
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clp_free_block(rrb);
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return rc;
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}
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int clp_add_pci_device(u32 fid, u32 fh, int configured)
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{
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struct zpci_dev *zdev;
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int rc = -ENOMEM;
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zpci_dbg(3, "add fid:%x, fh:%x, c:%d\n", fid, fh, configured);
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zdev = kzalloc(sizeof(*zdev), GFP_KERNEL);
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if (!zdev)
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goto error;
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zdev->fh = fh;
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zdev->fid = fid;
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/* Query function properties and update zdev */
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rc = clp_query_pci_fn(zdev, fh);
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if (rc)
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goto error;
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if (configured)
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zdev->state = ZPCI_FN_STATE_CONFIGURED;
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else
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zdev->state = ZPCI_FN_STATE_STANDBY;
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rc = zpci_create_device(zdev);
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if (rc)
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goto error;
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return 0;
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error:
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zpci_dbg(0, "add fid:%x, rc:%d\n", fid, rc);
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kfree(zdev);
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return rc;
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}
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/*
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* Enable/Disable a given PCI function defined by its function handle.
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*/
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static int clp_set_pci_fn(u32 *fh, u8 nr_dma_as, u8 command)
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{
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struct clp_req_rsp_set_pci *rrb;
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int rc, retries = 100;
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rrb = clp_alloc_block(GFP_KERNEL);
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if (!rrb)
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return -ENOMEM;
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do {
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memset(rrb, 0, sizeof(*rrb));
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rrb->request.hdr.len = sizeof(rrb->request);
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rrb->request.hdr.cmd = CLP_SET_PCI_FN;
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rrb->response.hdr.len = sizeof(rrb->response);
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rrb->request.fh = *fh;
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rrb->request.oc = command;
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rrb->request.ndas = nr_dma_as;
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rc = clp_req(rrb, CLP_LPS_PCI);
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if (rrb->response.hdr.rsp == CLP_RC_SETPCIFN_BUSY) {
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retries--;
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if (retries < 0)
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break;
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msleep(20);
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}
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} while (rrb->response.hdr.rsp == CLP_RC_SETPCIFN_BUSY);
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if (!rc && rrb->response.hdr.rsp == CLP_RC_OK)
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*fh = rrb->response.fh;
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else {
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zpci_err("Set PCI FN:\n");
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zpci_err_clp(rrb->response.hdr.rsp, rc);
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rc = -EIO;
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}
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clp_free_block(rrb);
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return rc;
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}
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int clp_enable_fh(struct zpci_dev *zdev, u8 nr_dma_as)
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{
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u32 fh = zdev->fh;
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int rc;
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rc = clp_set_pci_fn(&fh, nr_dma_as, CLP_SET_ENABLE_PCI_FN);
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zpci_dbg(3, "ena fid:%x, fh:%x, rc:%d\n", zdev->fid, fh, rc);
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if (rc)
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goto out;
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zdev->fh = fh;
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if (zdev->mio_capable) {
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rc = clp_set_pci_fn(&fh, nr_dma_as, CLP_SET_ENABLE_MIO);
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zpci_dbg(3, "ena mio fid:%x, fh:%x, rc:%d\n", zdev->fid, fh, rc);
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if (rc)
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clp_disable_fh(zdev);
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}
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out:
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return rc;
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}
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int clp_disable_fh(struct zpci_dev *zdev)
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{
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u32 fh = zdev->fh;
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int rc;
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if (!zdev_enabled(zdev))
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return 0;
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rc = clp_set_pci_fn(&fh, 0, CLP_SET_DISABLE_PCI_FN);
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zpci_dbg(3, "dis fid:%x, fh:%x, rc:%d\n", zdev->fid, fh, rc);
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if (!rc)
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zdev->fh = fh;
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return rc;
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}
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static int clp_list_pci(struct clp_req_rsp_list_pci *rrb, void *data,
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void (*cb)(struct clp_fh_list_entry *, void *))
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{
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u64 resume_token = 0;
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int entries, i, rc;
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do {
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memset(rrb, 0, sizeof(*rrb));
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rrb->request.hdr.len = sizeof(rrb->request);
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rrb->request.hdr.cmd = CLP_LIST_PCI;
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/* store as many entries as possible */
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rrb->response.hdr.len = CLP_BLK_SIZE - LIST_PCI_HDR_LEN;
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rrb->request.resume_token = resume_token;
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/* Get PCI function handle list */
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rc = clp_req(rrb, CLP_LPS_PCI);
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if (rc || rrb->response.hdr.rsp != CLP_RC_OK) {
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zpci_err("List PCI FN:\n");
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zpci_err_clp(rrb->response.hdr.rsp, rc);
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rc = -EIO;
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goto out;
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}
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update_uid_checking(rrb->response.uid_checking);
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WARN_ON_ONCE(rrb->response.entry_size !=
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sizeof(struct clp_fh_list_entry));
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entries = (rrb->response.hdr.len - LIST_PCI_HDR_LEN) /
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rrb->response.entry_size;
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resume_token = rrb->response.resume_token;
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for (i = 0; i < entries; i++)
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cb(&rrb->response.fh_list[i], data);
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} while (resume_token);
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out:
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return rc;
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}
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static void __clp_add(struct clp_fh_list_entry *entry, void *data)
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{
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struct zpci_dev *zdev;
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if (!entry->vendor_id)
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return;
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zdev = get_zdev_by_fid(entry->fid);
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if (!zdev)
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clp_add_pci_device(entry->fid, entry->fh, entry->config_state);
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}
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static void __clp_update(struct clp_fh_list_entry *entry, void *data)
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{
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struct zpci_dev *zdev;
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if (!entry->vendor_id)
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return;
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zdev = get_zdev_by_fid(entry->fid);
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if (!zdev)
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return;
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zdev->fh = entry->fh;
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}
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int clp_scan_pci_devices(void)
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{
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struct clp_req_rsp_list_pci *rrb;
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int rc;
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rrb = clp_alloc_block(GFP_KERNEL);
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if (!rrb)
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return -ENOMEM;
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rc = clp_list_pci(rrb, NULL, __clp_add);
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clp_free_block(rrb);
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return rc;
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}
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int clp_rescan_pci_devices(void)
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{
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struct clp_req_rsp_list_pci *rrb;
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int rc;
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zpci_remove_reserved_devices();
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rrb = clp_alloc_block(GFP_KERNEL);
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if (!rrb)
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return -ENOMEM;
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rc = clp_list_pci(rrb, NULL, __clp_add);
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clp_free_block(rrb);
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return rc;
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}
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int clp_rescan_pci_devices_simple(void)
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{
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struct clp_req_rsp_list_pci *rrb;
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int rc;
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rrb = clp_alloc_block(GFP_NOWAIT);
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if (!rrb)
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return -ENOMEM;
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rc = clp_list_pci(rrb, NULL, __clp_update);
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clp_free_block(rrb);
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return rc;
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}
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struct clp_state_data {
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u32 fid;
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enum zpci_state state;
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};
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static void __clp_get_state(struct clp_fh_list_entry *entry, void *data)
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{
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struct clp_state_data *sd = data;
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if (entry->fid != sd->fid)
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return;
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sd->state = entry->config_state;
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}
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int clp_get_state(u32 fid, enum zpci_state *state)
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{
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struct clp_req_rsp_list_pci *rrb;
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struct clp_state_data sd = {fid, ZPCI_FN_STATE_RESERVED};
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int rc;
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rrb = clp_alloc_block(GFP_ATOMIC);
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if (!rrb)
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return -ENOMEM;
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rc = clp_list_pci(rrb, &sd, __clp_get_state);
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if (!rc)
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*state = sd.state;
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clp_free_block(rrb);
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return rc;
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}
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static int clp_base_slpc(struct clp_req *req, struct clp_req_rsp_slpc *lpcb)
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{
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unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
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if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
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lpcb->response.hdr.len > limit)
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return -EINVAL;
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return clp_req(lpcb, CLP_LPS_BASE) ? -EOPNOTSUPP : 0;
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}
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static int clp_base_command(struct clp_req *req, struct clp_req_hdr *lpcb)
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{
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switch (lpcb->cmd) {
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case 0x0001: /* store logical-processor characteristics */
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return clp_base_slpc(req, (void *) lpcb);
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default:
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return -EINVAL;
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}
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}
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static int clp_pci_slpc(struct clp_req *req, struct clp_req_rsp_slpc *lpcb)
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{
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unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
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if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
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lpcb->response.hdr.len > limit)
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return -EINVAL;
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return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0;
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}
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static int clp_pci_list(struct clp_req *req, struct clp_req_rsp_list_pci *lpcb)
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{
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unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
|
|
|
|
if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
|
|
lpcb->response.hdr.len > limit)
|
|
return -EINVAL;
|
|
if (lpcb->request.reserved2 != 0)
|
|
return -EINVAL;
|
|
return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0;
|
|
}
|
|
|
|
static int clp_pci_query(struct clp_req *req,
|
|
struct clp_req_rsp_query_pci *lpcb)
|
|
{
|
|
unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
|
|
|
|
if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
|
|
lpcb->response.hdr.len > limit)
|
|
return -EINVAL;
|
|
if (lpcb->request.reserved2 != 0 || lpcb->request.reserved3 != 0)
|
|
return -EINVAL;
|
|
return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0;
|
|
}
|
|
|
|
static int clp_pci_query_grp(struct clp_req *req,
|
|
struct clp_req_rsp_query_pci_grp *lpcb)
|
|
{
|
|
unsigned long limit = PAGE_SIZE - sizeof(lpcb->request);
|
|
|
|
if (lpcb->request.hdr.len != sizeof(lpcb->request) ||
|
|
lpcb->response.hdr.len > limit)
|
|
return -EINVAL;
|
|
if (lpcb->request.reserved2 != 0 || lpcb->request.reserved3 != 0 ||
|
|
lpcb->request.reserved4 != 0)
|
|
return -EINVAL;
|
|
return clp_req(lpcb, CLP_LPS_PCI) ? -EOPNOTSUPP : 0;
|
|
}
|
|
|
|
static int clp_pci_command(struct clp_req *req, struct clp_req_hdr *lpcb)
|
|
{
|
|
switch (lpcb->cmd) {
|
|
case 0x0001: /* store logical-processor characteristics */
|
|
return clp_pci_slpc(req, (void *) lpcb);
|
|
case 0x0002: /* list PCI functions */
|
|
return clp_pci_list(req, (void *) lpcb);
|
|
case 0x0003: /* query PCI function */
|
|
return clp_pci_query(req, (void *) lpcb);
|
|
case 0x0004: /* query PCI function group */
|
|
return clp_pci_query_grp(req, (void *) lpcb);
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int clp_normal_command(struct clp_req *req)
|
|
{
|
|
struct clp_req_hdr *lpcb;
|
|
void __user *uptr;
|
|
int rc;
|
|
|
|
rc = -EINVAL;
|
|
if (req->lps != 0 && req->lps != 2)
|
|
goto out;
|
|
|
|
rc = -ENOMEM;
|
|
lpcb = clp_alloc_block(GFP_KERNEL);
|
|
if (!lpcb)
|
|
goto out;
|
|
|
|
rc = -EFAULT;
|
|
uptr = (void __force __user *)(unsigned long) req->data_p;
|
|
if (copy_from_user(lpcb, uptr, PAGE_SIZE) != 0)
|
|
goto out_free;
|
|
|
|
rc = -EINVAL;
|
|
if (lpcb->fmt != 0 || lpcb->reserved1 != 0 || lpcb->reserved2 != 0)
|
|
goto out_free;
|
|
|
|
switch (req->lps) {
|
|
case 0:
|
|
rc = clp_base_command(req, lpcb);
|
|
break;
|
|
case 2:
|
|
rc = clp_pci_command(req, lpcb);
|
|
break;
|
|
}
|
|
if (rc)
|
|
goto out_free;
|
|
|
|
rc = -EFAULT;
|
|
if (copy_to_user(uptr, lpcb, PAGE_SIZE) != 0)
|
|
goto out_free;
|
|
|
|
rc = 0;
|
|
|
|
out_free:
|
|
clp_free_block(lpcb);
|
|
out:
|
|
return rc;
|
|
}
|
|
|
|
static int clp_immediate_command(struct clp_req *req)
|
|
{
|
|
void __user *uptr;
|
|
unsigned long ilp;
|
|
int exists;
|
|
|
|
if (req->cmd > 1 || clp_get_ilp(&ilp) != 0)
|
|
return -EINVAL;
|
|
|
|
uptr = (void __force __user *)(unsigned long) req->data_p;
|
|
if (req->cmd == 0) {
|
|
/* Command code 0: test for a specific processor */
|
|
exists = test_bit_inv(req->lps, &ilp);
|
|
return put_user(exists, (int __user *) uptr);
|
|
}
|
|
/* Command code 1: return bit mask of installed processors */
|
|
return put_user(ilp, (unsigned long __user *) uptr);
|
|
}
|
|
|
|
static long clp_misc_ioctl(struct file *filp, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
struct clp_req req;
|
|
void __user *argp;
|
|
|
|
if (cmd != CLP_SYNC)
|
|
return -EINVAL;
|
|
|
|
argp = is_compat_task() ? compat_ptr(arg) : (void __user *) arg;
|
|
if (copy_from_user(&req, argp, sizeof(req)))
|
|
return -EFAULT;
|
|
if (req.r != 0)
|
|
return -EINVAL;
|
|
return req.c ? clp_immediate_command(&req) : clp_normal_command(&req);
|
|
}
|
|
|
|
static int clp_misc_release(struct inode *inode, struct file *filp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct file_operations clp_misc_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = nonseekable_open,
|
|
.release = clp_misc_release,
|
|
.unlocked_ioctl = clp_misc_ioctl,
|
|
.compat_ioctl = clp_misc_ioctl,
|
|
.llseek = no_llseek,
|
|
};
|
|
|
|
static struct miscdevice clp_misc_device = {
|
|
.minor = MISC_DYNAMIC_MINOR,
|
|
.name = "clp",
|
|
.fops = &clp_misc_fops,
|
|
};
|
|
|
|
static int __init clp_misc_init(void)
|
|
{
|
|
return misc_register(&clp_misc_device);
|
|
}
|
|
|
|
device_initcall(clp_misc_init);
|