Ezequiel Garcia e0b7a79524 clk: pistachio: Lock the PLL when enabled upon rate change ... Currently, when the rate is changed, the driver makes sure the PLL is enabled before doing so. This is done because the PLL cannot be locked while disabled. Once locked, the drivers returns the PLL to its previous enable/disable state. This is a bit cumbersome, and can be simplified. This commit reworks the .set_rate() functions for the integer and fractional PLLs. Upon rate change, the PLL is now locked only if it's already enabled. Also, the driver locks the PLL on .enable(). This makes sure the PLL is locked when enabled, and not locked when disabled. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2015-06-04 12:43:33 -07:00
..
clk-pistachio.c	CLK: Pistachio: Register external clock gates	2015-03-31 11:59:31 +02:00
clk-pll.c	clk: pistachio: Lock the PLL when enabled upon rate change	2015-06-04 12:43:33 -07:00
clk.c
clk.h
Makefile	CLK: Pistachio: Register core clocks	2015-03-31 11:59:10 +02:00