a5eb8bbd66
This patch resurrects an old never-finished driver for Toshiba PCI SD controllers found in some older Toshiba laptops (such as Portege R100): 02:0d.0 System peripheral [0880]: Toshiba America Info Systems SD TypA Controller [1179:0805] (rev 05) The code is fixed, cleaned up and successfully tested with SD, SDHC, SDXC and MMC cards on Portege R100. (MMC cards don't even work in Windows!) SDIO probably does not work (don't have any SDIO card). The hardware is slow (around 2 MB/s - same in Windows) because it does not support bus mastering (busmaster enable bit cannot be set in PCI control reg). Also the card clock is limited to 16MHz (33MHz PCI clock divided by 2). Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
177 lines
6.1 KiB
C
177 lines
6.1 KiB
C
/*
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* Toshiba PCI Secure Digital Host Controller Interface driver
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*
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* Copyright (C) 2014 Ondrej Zary
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* Copyright (C) 2007 Richard Betts, All Rights Reserved.
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*
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* Based on asic3_mmc.c Copyright (c) 2005 SDG Systems, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#define HCLK 33000000 /* 33 MHz (PCI clock) */
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#define SD_PCICFG_CLKSTOP 0x40 /* 0x1f = clock controller, 0 = stop */
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#define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
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#define SD_PCICFG_CLKMODE 0x42 /* Control clock of SD controller */
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#define SD_PCICFG_PINSTATUS 0x44 /* R/O: read status of SD pins */
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#define SD_PCICFG_POWER1 0x48
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#define SD_PCICFG_POWER2 0x49
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#define SD_PCICFG_POWER3 0x4a
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#define SD_PCICFG_CARDDETECT 0x4c
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#define SD_PCICFG_SLOTS 0x50 /* R/O: define support slot number */
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#define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
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#define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
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#define SD_PCICFG_EXTGATECLK3 0xf9 /* Bit 1: double buffer/single buffer */
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#define SD_PCICFG_SDLED_ENABLE1 0xfa
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#define SD_PCICFG_SDLED_ENABLE2 0xfe
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#define SD_PCICFG_CLKMODE_DIV_DISABLE BIT(0)
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#define SD_PCICFG_CLKSTOP_ENABLE_ALL 0x1f
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#define SD_PCICFG_LED_ENABLE1_START 0x12
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#define SD_PCICFG_LED_ENABLE2_START 0x80
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#define SD_PCICFG_PWR1_33V 0x08 /* Set for 3.3 volts */
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#define SD_PCICFG_PWR1_OFF 0x00 /* Turn off power */
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#define SD_PCICFG_PWR2_AUTO 0x02
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#define SD_CMD 0x00 /* also for SDIO */
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#define SD_ARG0 0x04 /* also for SDIO */
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#define SD_ARG1 0x06 /* also for SDIO */
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#define SD_STOPINTERNAL 0x08
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#define SD_BLOCKCOUNT 0x0a /* also for SDIO */
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#define SD_RESPONSE0 0x0c /* also for SDIO */
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#define SD_RESPONSE1 0x0e /* also for SDIO */
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#define SD_RESPONSE2 0x10 /* also for SDIO */
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#define SD_RESPONSE3 0x12 /* also for SDIO */
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#define SD_RESPONSE4 0x14 /* also for SDIO */
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#define SD_RESPONSE5 0x16 /* also for SDIO */
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#define SD_RESPONSE6 0x18 /* also for SDIO */
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#define SD_RESPONSE7 0x1a /* also for SDIO */
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#define SD_CARDSTATUS 0x1c /* also for SDIO */
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#define SD_BUFFERCTRL 0x1e /* also for SDIO */
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#define SD_INTMASKCARD 0x20 /* also for SDIO */
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#define SD_INTMASKBUFFER 0x22 /* also for SDIO */
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#define SD_CARDCLOCKCTRL 0x24
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#define SD_CARDXFERDATALEN 0x26 /* also for SDIO */
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#define SD_CARDOPTIONSETUP 0x28 /* also for SDIO */
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#define SD_ERRORSTATUS0 0x2c /* also for SDIO */
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#define SD_ERRORSTATUS1 0x2e /* also for SDIO */
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#define SD_DATAPORT 0x30 /* also for SDIO */
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#define SD_TRANSACTIONCTRL 0x34 /* also for SDIO */
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#define SD_SOFTWARERESET 0xe0 /* also for SDIO */
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/* registers above marked "also for SDIO" and all SDIO registers below can be
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* accessed at SDIO_BASE + reg address */
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#define SDIO_BASE 0x100
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#define SDIO_CARDPORTSEL 0x02
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#define SDIO_CARDINTCTRL 0x36
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#define SDIO_CLOCKNWAITCTRL 0x38
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#define SDIO_HOSTINFORMATION 0x3a
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#define SDIO_ERRORCTRL 0x3c
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#define SDIO_LEDCTRL 0x3e
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#define SD_TRANSCTL_SET BIT(8)
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#define SD_CARDCLK_DIV_DISABLE BIT(15)
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#define SD_CARDCLK_ENABLE_CLOCK BIT(8)
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#define SD_CARDCLK_CLK_DIV_512 BIT(7)
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#define SD_CARDCLK_CLK_DIV_256 BIT(6)
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#define SD_CARDCLK_CLK_DIV_128 BIT(5)
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#define SD_CARDCLK_CLK_DIV_64 BIT(4)
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#define SD_CARDCLK_CLK_DIV_32 BIT(3)
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#define SD_CARDCLK_CLK_DIV_16 BIT(2)
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#define SD_CARDCLK_CLK_DIV_8 BIT(1)
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#define SD_CARDCLK_CLK_DIV_4 BIT(0)
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#define SD_CARDCLK_CLK_DIV_2 0
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#define SD_CARDOPT_REQUIRED 0x000e
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#define SD_CARDOPT_DATA_RESP_TIMEOUT(x) (((x) & 0x0f) << 4) /* 4 bits */
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#define SD_CARDOPT_C2_MODULE_ABSENT BIT(14)
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#define SD_CARDOPT_DATA_XFR_WIDTH_1 (1 << 15)
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#define SD_CARDOPT_DATA_XFR_WIDTH_4 (0 << 15)
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#define SD_CMD_TYPE_CMD (0 << 6)
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#define SD_CMD_TYPE_ACMD (1 << 6)
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#define SD_CMD_TYPE_AUTHEN (2 << 6)
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#define SD_CMD_RESP_TYPE_NONE (3 << 8)
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#define SD_CMD_RESP_TYPE_EXT_R1 (4 << 8)
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#define SD_CMD_RESP_TYPE_EXT_R1B (5 << 8)
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#define SD_CMD_RESP_TYPE_EXT_R2 (6 << 8)
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#define SD_CMD_RESP_TYPE_EXT_R3 (7 << 8)
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#define SD_CMD_RESP_TYPE_EXT_R6 (4 << 8)
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#define SD_CMD_RESP_TYPE_EXT_R7 (4 << 8)
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#define SD_CMD_DATA_PRESENT BIT(11)
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#define SD_CMD_TRANSFER_READ BIT(12)
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#define SD_CMD_MULTI_BLOCK BIT(13)
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#define SD_CMD_SECURITY_CMD BIT(14)
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#define SD_STOPINT_ISSUE_CMD12 BIT(0)
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#define SD_STOPINT_AUTO_ISSUE_CMD12 BIT(8)
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#define SD_CARD_RESP_END BIT(0)
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#define SD_CARD_RW_END BIT(2)
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#define SD_CARD_CARD_REMOVED_0 BIT(3)
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#define SD_CARD_CARD_INSERTED_0 BIT(4)
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#define SD_CARD_PRESENT_0 BIT(5)
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#define SD_CARD_UNK6 BIT(6)
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#define SD_CARD_WRITE_PROTECT BIT(7)
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#define SD_CARD_CARD_REMOVED_3 BIT(8)
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#define SD_CARD_CARD_INSERTED_3 BIT(9)
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#define SD_CARD_PRESENT_3 BIT(10)
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#define SD_BUF_CMD_INDEX_ERR BIT(16)
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#define SD_BUF_CRC_ERR BIT(17)
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#define SD_BUF_STOP_BIT_END_ERR BIT(18)
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#define SD_BUF_DATA_TIMEOUT BIT(19)
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#define SD_BUF_OVERFLOW BIT(20)
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#define SD_BUF_UNDERFLOW BIT(21)
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#define SD_BUF_CMD_TIMEOUT BIT(22)
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#define SD_BUF_UNK7 BIT(23)
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#define SD_BUF_READ_ENABLE BIT(24)
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#define SD_BUF_WRITE_ENABLE BIT(25)
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#define SD_BUF_ILLEGAL_FUNCTION BIT(29)
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#define SD_BUF_CMD_BUSY BIT(30)
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#define SD_BUF_ILLEGAL_ACCESS BIT(31)
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#define SD_ERR0_RESP_CMD_ERR BIT(0)
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#define SD_ERR0_RESP_NON_CMD12_END_BIT_ERR BIT(2)
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#define SD_ERR0_RESP_CMD12_END_BIT_ERR BIT(3)
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#define SD_ERR0_READ_DATA_END_BIT_ERR BIT(4)
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#define SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR BIT(5)
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#define SD_ERR0_RESP_NON_CMD12_CRC_ERR BIT(8)
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#define SD_ERR0_RESP_CMD12_CRC_ERR BIT(9)
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#define SD_ERR0_READ_DATA_CRC_ERR BIT(10)
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#define SD_ERR0_WRITE_CMD_CRC_ERR BIT(11)
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#define SD_ERR1_NO_CMD_RESP BIT(16)
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#define SD_ERR1_TIMEOUT_READ_DATA BIT(20)
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#define SD_ERR1_TIMEOUT_CRS_STATUS BIT(21)
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#define SD_ERR1_TIMEOUT_CRC_BUSY BIT(22)
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#define IRQ_DONT_CARE_BITS (SD_CARD_PRESENT_3 \
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| SD_CARD_WRITE_PROTECT \
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| SD_CARD_UNK6 \
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| SD_CARD_PRESENT_0 \
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| SD_BUF_UNK7 \
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| SD_BUF_CMD_BUSY)
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struct toshsd_host {
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struct pci_dev *pdev;
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struct mmc_host *mmc;
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spinlock_t lock;
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struct mmc_request *mrq;/* Current request */
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struct mmc_command *cmd;/* Current command */
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struct mmc_data *data; /* Current data request */
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struct sg_mapping_iter sg_miter; /* for PIO */
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void __iomem *ioaddr; /* mapped address */
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};
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