4866cde064
Instead of requiring architecture code to interact with the scheduler's locking implementation, provide a couple of defines that can be used by the architecture to request runqueue unlocked context switches, and ask for interrupts to be enabled over the context switch. Also replaces the "switch_lock" used by these architectures with an oncpu flag (note, not a potentially slow bitflag). This eliminates one bus locked memory operation when context switching, and simplifies the task_running function. Signed-off-by: Nick Piggin <nickpiggin@yahoo.com.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
476 lines
13 KiB
C
476 lines
13 KiB
C
/*
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* include/asm-s390/system.h
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*
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* S390 version
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* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
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*
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* Derived from "include/asm-i386/system.h"
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*/
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#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <asm/types.h>
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#include <asm/ptrace.h>
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#include <asm/setup.h>
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#include <asm/processor.h>
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#ifdef __KERNEL__
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struct task_struct;
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extern struct task_struct *__switch_to(void *, void *);
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#ifdef __s390x__
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#define __FLAG_SHIFT 56
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#else /* ! __s390x__ */
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#define __FLAG_SHIFT 24
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#endif /* ! __s390x__ */
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static inline void save_fp_regs(s390_fp_regs *fpregs)
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{
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asm volatile (
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" std 0,8(%1)\n"
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" std 2,24(%1)\n"
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" std 4,40(%1)\n"
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" std 6,56(%1)"
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: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" stfpc 0(%1)\n"
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" std 1,16(%1)\n"
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" std 3,32(%1)\n"
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" std 5,48(%1)\n"
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" std 7,64(%1)\n"
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" std 8,72(%1)\n"
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" std 9,80(%1)\n"
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" std 10,88(%1)\n"
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" std 11,96(%1)\n"
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" std 12,104(%1)\n"
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" std 13,112(%1)\n"
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" std 14,120(%1)\n"
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" std 15,128(%1)\n"
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: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
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}
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static inline void restore_fp_regs(s390_fp_regs *fpregs)
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{
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asm volatile (
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" ld 0,8(%0)\n"
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" ld 2,24(%0)\n"
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" ld 4,40(%0)\n"
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" ld 6,56(%0)"
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: : "a" (fpregs), "m" (*fpregs) );
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" lfpc 0(%0)\n"
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" ld 1,16(%0)\n"
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" ld 3,32(%0)\n"
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" ld 5,48(%0)\n"
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" ld 7,64(%0)\n"
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" ld 8,72(%0)\n"
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" ld 9,80(%0)\n"
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" ld 10,88(%0)\n"
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" ld 11,96(%0)\n"
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" ld 12,104(%0)\n"
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" ld 13,112(%0)\n"
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" ld 14,120(%0)\n"
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" ld 15,128(%0)\n"
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: : "a" (fpregs), "m" (*fpregs) );
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}
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static inline void save_access_regs(unsigned int *acrs)
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{
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asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
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}
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static inline void restore_access_regs(unsigned int *acrs)
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{
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asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
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}
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#define switch_to(prev,next,last) do { \
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if (prev == next) \
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break; \
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save_fp_regs(&prev->thread.fp_regs); \
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restore_fp_regs(&next->thread.fp_regs); \
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save_access_regs(&prev->thread.acrs[0]); \
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restore_access_regs(&next->thread.acrs[0]); \
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prev = __switch_to(prev,next); \
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} while (0)
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#ifdef CONFIG_VIRT_CPU_ACCOUNTING
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extern void account_user_vtime(struct task_struct *);
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extern void account_system_vtime(struct task_struct *);
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#else
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#define account_system_vtime(prev) do { } while (0)
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#endif
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#define finish_arch_switch(rq, prev) do { \
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set_fs(current->thread.mm_segment); \
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account_system_vtime(prev); \
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} while (0)
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#define nop() __asm__ __volatile__ ("nop")
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))
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static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
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{
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unsigned long addr, old;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,0(%4)\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,0(%4)\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(int *) addr)
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: "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
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"m" (*(int *) addr) : "memory", "cc", "0" );
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x = old >> shift;
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break;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,0(%4)\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,0(%4)\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(int *) addr)
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: "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
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"m" (*(int *) addr) : "memory", "cc", "0" );
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x = old >> shift;
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break;
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case 4:
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asm volatile (
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" l %0,0(%3)\n"
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"0: cs %0,%2,0(%3)\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(int *) ptr)
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: "d" (x), "a" (ptr), "m" (*(int *) ptr)
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: "memory", "cc" );
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x = old;
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break;
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#ifdef __s390x__
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case 8:
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asm volatile (
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" lg %0,0(%3)\n"
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"0: csg %0,%2,0(%3)\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(long *) ptr)
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: "d" (x), "a" (ptr), "m" (*(long *) ptr)
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: "memory", "cc" );
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x = old;
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break;
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#endif /* __s390x__ */
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}
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return x;
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}
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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#define cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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unsigned long addr, prev, tmp;
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int shift;
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switch (size) {
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case 1:
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addr = (unsigned long) ptr;
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,0(%4)\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%2\n"
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" or %1,%3\n"
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" cs %0,%1,0(%4)\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp)
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: "d" (old << shift), "d" (new << shift), "a" (ptr),
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"d" (~(255 << shift))
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: "memory", "cc" );
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return prev >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,0(%4)\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%2\n"
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" or %1,%3\n"
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" cs %0,%1,0(%4)\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp)
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: "d" (old << shift), "d" (new << shift), "a" (ptr),
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"d" (~(65535 << shift))
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: "memory", "cc" );
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return prev >> shift;
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case 4:
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asm volatile (
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" cs %0,%2,0(%3)\n"
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: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
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: "memory", "cc" );
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return prev;
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#ifdef __s390x__
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case 8:
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asm volatile (
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" csg %0,%2,0(%3)\n"
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: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
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: "memory", "cc" );
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return prev;
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#endif /* __s390x__ */
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}
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return old;
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}
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*
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* This is very similar to the ppc eieio/sync instruction in that is
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* does a checkpoint syncronisation & makes sure that
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* all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
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*/
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#define eieio() __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
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# define SYNC_OTHER_CORES(x) eieio()
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#define mb() eieio()
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#define rmb() eieio()
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#define wmb() eieio()
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#define read_barrier_depends() do { } while(0)
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() smp_mb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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/* interrupt control.. */
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#define local_irq_enable() ({ \
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unsigned long __dummy; \
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__asm__ __volatile__ ( \
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"stosm 0(%1),0x03" \
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: "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
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})
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#define local_irq_disable() ({ \
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unsigned long __flags; \
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__asm__ __volatile__ ( \
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"stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
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__flags; \
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})
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#define local_save_flags(x) \
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__asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )
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#define local_irq_restore(x) \
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__asm__ __volatile__("ssm 0(%0)" : : "a" (&x), "m" (x) : "memory")
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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!((flags >> __FLAG_SHIFT) & 3); \
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})
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#ifdef __s390x__
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" \
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" lctlg 0,0,0(%0)\n" \
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"0: ex %1,0(1)" \
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: : "a" (&array), "a" (((low)<<4)+(high)), \
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"m" (*(addrtype *)(array)) : "1" ); \
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})
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" \
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" stctg 0,0,0(%1)\n" \
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"0: ex %2,0(1)" \
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: "=m" (*(addrtype *)(array)) \
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: "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
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})
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#define __ctl_set_bit(cr, bit) ({ \
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__u8 __dummy[24]; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" /* skip indirect insns */ \
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" stctg 0,0,0(%1)\n" \
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" lctlg 0,0,0(%1)\n" \
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"0: ex %2,0(1)\n" /* execute stctl */ \
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" lg 0,0(%1)\n" \
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" ogr 0,%3\n" /* set the bit */ \
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" stg 0,0(%1)\n" \
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"1: ex %2,6(1)" /* execute lctl */ \
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: "=m" (__dummy) \
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: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
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"a" (cr*17), "a" (1L<<(bit)) \
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: "cc", "0", "1" ); \
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})
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#define __ctl_clear_bit(cr, bit) ({ \
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__u8 __dummy[16]; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" /* skip indirect insns */ \
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" stctg 0,0,0(%1)\n" \
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" lctlg 0,0,0(%1)\n" \
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"0: ex %2,0(1)\n" /* execute stctl */ \
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" lg 0,0(%1)\n" \
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" ngr 0,%3\n" /* set the bit */ \
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" stg 0,0(%1)\n" \
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"1: ex %2,6(1)" /* execute lctl */ \
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: "=m" (__dummy) \
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: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
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"a" (cr*17), "a" (~(1L<<(bit))) \
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: "cc", "0", "1" ); \
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})
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#else /* __s390x__ */
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" \
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" lctl 0,0,0(%0)\n" \
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"0: ex %1,0(1)" \
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: : "a" (&array), "a" (((low)<<4)+(high)), \
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"m" (*(addrtype *)(array)) : "1" ); \
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})
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" \
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" stctl 0,0,0(%1)\n" \
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"0: ex %2,0(1)" \
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: "=m" (*(addrtype *)(array)) \
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: "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
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})
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#define __ctl_set_bit(cr, bit) ({ \
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__u8 __dummy[16]; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" /* skip indirect insns */ \
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" stctl 0,0,0(%1)\n" \
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" lctl 0,0,0(%1)\n" \
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"0: ex %2,0(1)\n" /* execute stctl */ \
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" l 0,0(%1)\n" \
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" or 0,%3\n" /* set the bit */ \
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" st 0,0(%1)\n" \
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"1: ex %2,4(1)" /* execute lctl */ \
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: "=m" (__dummy) \
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: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
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"a" (cr*17), "a" (1<<(bit)) \
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: "cc", "0", "1" ); \
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})
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#define __ctl_clear_bit(cr, bit) ({ \
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__u8 __dummy[16]; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" /* skip indirect insns */ \
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" stctl 0,0,0(%1)\n" \
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" lctl 0,0,0(%1)\n" \
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"0: ex %2,0(1)\n" /* execute stctl */ \
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" l 0,0(%1)\n" \
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" nr 0,%3\n" /* set the bit */ \
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" st 0,0(%1)\n" \
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"1: ex %2,4(1)" /* execute lctl */ \
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: "=m" (__dummy) \
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: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
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"a" (cr*17), "a" (~(1<<(bit))) \
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: "cc", "0", "1" ); \
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})
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#endif /* __s390x__ */
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/* For spinlocks etc */
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#define local_irq_save(x) ((x) = local_irq_disable())
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/*
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* Use to set psw mask except for the first byte which
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* won't be changed by this function.
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*/
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static inline void
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__set_psw_mask(unsigned long mask)
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{
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local_save_flags(mask);
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__load_psw_mask(mask);
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}
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#define local_mcck_enable() __set_psw_mask(PSW_KERNEL_BITS)
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#define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
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#ifdef CONFIG_SMP
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extern void smp_ctl_set_bit(int cr, int bit);
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extern void smp_ctl_clear_bit(int cr, int bit);
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#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
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#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
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#else
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#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
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#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
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#endif /* CONFIG_SMP */
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extern void (*_machine_restart)(char *command);
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extern void (*_machine_halt)(void);
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extern void (*_machine_power_off)(void);
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif
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