73a59c1c4a
Patch from SAN People Following changes were made to clock.c: 1) Replaced <asm/hardware/clock.h> with <linux/clk.h> 2) Removed old unused clk_enable & clk_disable. 3) Replaced clk_use/clk_unuse with clk_enable/clk_disable. Otherwise it's the same as the previous patch. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
621 lines
14 KiB
C
621 lines
14 KiB
C
/*
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* linux/arch/arm/mach-at91rm9200/clock.c
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*
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* Copyright (C) 2005 David Brownell
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* Copyright (C) 2005 Ivan Kokshaysky
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/fs.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <asm/semaphore.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/board.h> /* for master clock global */
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#include "generic.h"
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#undef DEBUG
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/*
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* There's a lot more which can be done with clocks, including cpufreq
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* integration, slow clock mode support (for system suspend), letting
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* PLLB be used at other rates (on boards that don't need USB), etc.
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*/
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struct clk {
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const char *name;
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unsigned long rate_hz;
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struct clk *parent;
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u32 pmc_mask;
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void (*mode)(struct clk *, int);
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unsigned id:2; /* PCK0..3, or 32k/main/a/b */
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unsigned primary:1;
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unsigned pll:1;
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unsigned programmable:1;
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u16 users;
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};
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static spinlock_t clk_lock;
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static u32 at91_pllb_usb_init;
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/*
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* Four primary clock sources: two crystal oscillators (32K, main), and
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* two PLLs. PLLA usually runs the master clock; and PLLB must run at
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* 48 MHz (unless no USB function clocks are needed). The main clock and
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* both PLLs are turned off to run in "slow clock mode" (system suspend).
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*/
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static struct clk clk32k = {
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.name = "clk32k",
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.rate_hz = AT91_SLOW_CLOCK,
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.users = 1, /* always on */
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.id = 0,
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.primary = 1,
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};
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static struct clk main_clk = {
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.name = "main",
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.pmc_mask = 1 << 0, /* in PMC_SR */
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.users = 1,
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.id = 1,
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.primary = 1,
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};
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static struct clk plla = {
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.name = "plla",
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.parent = &main_clk,
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.pmc_mask = 1 << 1, /* in PMC_SR */
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.id = 2,
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.primary = 1,
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.pll = 1,
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};
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static void pllb_mode(struct clk *clk, int is_on)
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{
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u32 value;
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if (is_on) {
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is_on = AT91_PMC_LOCKB;
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value = at91_pllb_usb_init;
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} else
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value = 0;
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at91_sys_write(AT91_CKGR_PLLBR, value);
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do {
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cpu_relax();
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} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
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}
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static struct clk pllb = {
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.name = "pllb",
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.parent = &main_clk,
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.pmc_mask = 1 << 2, /* in PMC_SR */
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.mode = pllb_mode,
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.id = 3,
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.primary = 1,
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.pll = 1,
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};
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static void pmc_sys_mode(struct clk *clk, int is_on)
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{
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if (is_on)
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at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
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else
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at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
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}
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/* USB function clocks (PLLB must be 48 MHz) */
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static struct clk udpck = {
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.name = "udpck",
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.parent = &pllb,
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.pmc_mask = AT91_PMC_UDP,
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.mode = pmc_sys_mode,
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};
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static struct clk uhpck = {
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.name = "uhpck",
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.parent = &pllb,
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.pmc_mask = AT91_PMC_UHP,
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.mode = pmc_sys_mode,
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};
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#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
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/*
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* The four programmable clocks can be parented by any primary clock.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.mode = pmc_sys_mode,
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.programmable = 1,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.mode = pmc_sys_mode,
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.programmable = 1,
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.id = 1,
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};
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static struct clk pck2 = {
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.name = "pck2",
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.pmc_mask = AT91_PMC_PCK2,
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.mode = pmc_sys_mode,
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.programmable = 1,
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.id = 2,
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};
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static struct clk pck3 = {
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.name = "pck3",
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.pmc_mask = AT91_PMC_PCK3,
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.mode = pmc_sys_mode,
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.programmable = 1,
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.id = 3,
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};
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#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
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/*
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* The master clock is divided from the CPU clock (by 1-4). It's used for
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* memory, interfaces to on-chip peripherals, the AIC, and sometimes more
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* (e.g baud rate generation). It's sourced from one of the primary clocks.
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*/
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static struct clk mck = {
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.name = "mck",
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.pmc_mask = 1 << 3, /* in PMC_SR */
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.users = 1, /* (must be) always on */
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};
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static void pmc_periph_mode(struct clk *clk, int is_on)
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{
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if (is_on)
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at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
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else
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at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
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}
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static struct clk udc_clk = {
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.name = "udc_clk",
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.parent = &mck,
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.pmc_mask = 1 << AT91_ID_UDP,
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.mode = pmc_periph_mode,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.parent = &mck,
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.pmc_mask = 1 << AT91_ID_UHP,
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.mode = pmc_periph_mode,
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};
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static struct clk *const clock_list[] = {
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/* four primary clocks -- MUST BE FIRST! */
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&clk32k,
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&main_clk,
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&plla,
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&pllb,
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/* PLLB children (USB) */
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&udpck,
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&uhpck,
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#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
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/* programmable clocks */
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&pck0,
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&pck1,
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&pck2,
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&pck3,
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#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
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/* MCK and peripherals */
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&mck,
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// usart0..usart3
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// mmc
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&udc_clk,
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// i2c
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// spi
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// ssc0..ssc2
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// tc0..tc5
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&ohci_clk,
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// ether
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};
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/* clocks are all static for now; no refcounting necessary */
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struct clk *clk_get(struct device *dev, const char *id)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
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if (strcmp(id, clock_list[i]->name) == 0)
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return clock_list[i];
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}
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return ERR_PTR(-ENOENT);
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}
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EXPORT_SYMBOL(clk_get);
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void clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_put);
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static void __clk_enable(struct clk *clk)
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{
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if (clk->parent)
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__clk_enable(clk->parent);
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if (clk->users++ == 0 && clk->mode)
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clk->mode(clk, 1);
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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spin_lock_irqsave(&clk_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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static void __clk_disable(struct clk *clk)
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{
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BUG_ON(clk->users == 0);
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if (--clk->users == 0 && clk->mode)
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clk->mode(clk, 0);
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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spin_lock_irqsave(&clk_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clk_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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unsigned long flags;
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unsigned long rate;
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spin_lock_irqsave(&clk_lock, flags);
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for (;;) {
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rate = clk->rate_hz;
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if (rate || !clk->parent)
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break;
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clk = clk->parent;
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}
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spin_unlock_irqrestore(&clk_lock, flags);
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return rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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/*------------------------------------------------------------------------*/
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#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
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/*
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* For now, only the programmable clocks support reparenting (MCK could
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* do this too, with care) or rate changing (the PLLs could do this too,
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* ditto MCK but that's more for cpufreq). Drivers may reparent to get
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* a better rate match; we don't.
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*/
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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unsigned prescale;
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unsigned long actual;
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if (!clk->programmable)
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return -EINVAL;
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spin_lock_irqsave(&clk_lock, flags);
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actual = clk->parent->rate_hz;
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for (prescale = 0; prescale < 7; prescale++) {
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if (actual && actual <= rate)
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break;
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actual >>= 1;
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}
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spin_unlock_irqrestore(&clk_lock, flags);
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return (prescale < 7) ? actual : -ENOENT;
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}
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EXPORT_SYMBOL(clk_round_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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unsigned prescale;
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unsigned long actual;
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if (!clk->programmable)
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return -EINVAL;
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if (clk->users)
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return -EBUSY;
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spin_lock_irqsave(&clk_lock, flags);
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actual = clk->parent->rate_hz;
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for (prescale = 0; prescale < 7; prescale++) {
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if (actual && actual <= rate) {
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u32 pckr;
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pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
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pckr &= 0x03;
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pckr |= prescale << 2;
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at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
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clk->rate_hz = actual;
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break;
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}
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actual >>= 1;
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}
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spin_unlock_irqrestore(&clk_lock, flags);
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return (prescale < 7) ? actual : -ENOENT;
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}
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EXPORT_SYMBOL(clk_set_rate);
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struct clk *clk_get_parent(struct clk *clk)
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{
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return clk->parent;
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}
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EXPORT_SYMBOL(clk_get_parent);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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if (clk->users)
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return -EBUSY;
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if (!parent->primary || !clk->programmable)
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return -EINVAL;
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spin_lock_irqsave(&clk_lock, flags);
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clk->rate_hz = parent->rate_hz;
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clk->parent = parent;
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at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
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/*------------------------------------------------------------------------*/
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#ifdef CONFIG_DEBUG_FS
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static int at91_clk_show(struct seq_file *s, void *unused)
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{
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u32 scsr, pcsr, sr;
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unsigned i;
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seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
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seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
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seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
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seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
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seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
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seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
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seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
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for (i = 0; i < 4; i++)
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seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
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seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
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seq_printf(s, "\n");
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for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
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char *state;
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struct clk *clk = clock_list[i];
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if (clk->mode == pmc_sys_mode)
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state = (scsr & clk->pmc_mask) ? "on" : "off";
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else if (clk->mode == pmc_periph_mode)
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state = (pcsr & clk->pmc_mask) ? "on" : "off";
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else if (clk->pmc_mask)
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state = (sr & clk->pmc_mask) ? "on" : "off";
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else if (clk == &clk32k || clk == &main_clk)
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state = "on";
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else
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state = "";
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seq_printf(s, "%-10s users=%d %-3s %9ld Hz %s\n",
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clk->name, clk->users, state, clk_get_rate(clk),
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clk->parent ? clk->parent->name : "");
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}
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return 0;
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}
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static int at91_clk_open(struct inode *inode, struct file *file)
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{
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return single_open(file, at91_clk_show, NULL);
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}
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static struct file_operations at91_clk_operations = {
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.open = at91_clk_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int __init at91_clk_debugfs_init(void)
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{
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/* /sys/kernel/debug/at91_clk */
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(void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
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return 0;
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}
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postcore_initcall(at91_clk_debugfs_init);
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#endif
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/*------------------------------------------------------------------------*/
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static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
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{
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unsigned mul, div;
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div = reg & 0xff;
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mul = (reg >> 16) & 0x7ff;
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if (div && mul) {
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freq /= div;
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freq *= mul + 1;
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} else
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freq = 0;
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if (pll == &pllb && (reg & (1 << 28)))
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freq /= 2;
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return freq;
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}
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static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
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{
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unsigned i, div = 0, mul = 0, diff = 1 << 30;
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unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
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/* PLL output max 240 MHz (or 180 MHz per errata) */
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if (out_freq > 240000000)
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goto fail;
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for (i = 1; i < 256; i++) {
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int diff1;
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unsigned input, mul1;
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/*
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* PLL input between 1MHz and 32MHz per spec, but lower
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* frequences seem necessary in some cases so allow 100K.
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*/
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input = main_freq / i;
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if (input < 100000)
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continue;
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if (input > 32000000)
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continue;
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mul1 = out_freq / input;
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if (mul1 > 2048)
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continue;
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if (mul1 < 2)
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goto fail;
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diff1 = out_freq - input * mul1;
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if (diff1 < 0)
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diff1 = -diff1;
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if (diff > diff1) {
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diff = diff1;
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div = i;
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mul = mul1;
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if (diff == 0)
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break;
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}
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}
|
|
if (i == 256 && diff > (out_freq >> 5))
|
|
goto fail;
|
|
return ret | ((mul - 1) << 16) | div;
|
|
fail:
|
|
return 0;
|
|
}
|
|
|
|
int __init at91_clock_init(unsigned long main_clock)
|
|
{
|
|
unsigned tmp, freq, mckr;
|
|
|
|
spin_lock_init(&clk_lock);
|
|
|
|
/*
|
|
* When the bootloader initialized the main oscillator correctly,
|
|
* there's no problem using the cycle counter. But if it didn't,
|
|
* or when using oscillator bypass mode, we must be told the speed
|
|
* of the main clock.
|
|
*/
|
|
if (!main_clock) {
|
|
do {
|
|
tmp = at91_sys_read(AT91_CKGR_MCFR);
|
|
} while (!(tmp & 0x10000));
|
|
main_clock = (tmp & 0xffff) * (AT91_SLOW_CLOCK / 16);
|
|
}
|
|
main_clk.rate_hz = main_clock;
|
|
|
|
/* report if PLLA is more than mildly overclocked */
|
|
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
|
|
if (plla.rate_hz > 209000000)
|
|
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
|
|
|
/*
|
|
* USB clock init: choose 48 MHz PLLB value, turn all clocks off,
|
|
* disable 48MHz clock during usb peripheral suspend.
|
|
*
|
|
* REVISIT: assumes MCK doesn't derive from PLLB!
|
|
*/
|
|
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | 0x10000000;
|
|
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
|
|
at91_sys_write(AT91_PMC_PCDR, (1 << AT91_ID_UHP) | (1 << AT91_ID_UDP));
|
|
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
|
|
at91_sys_write(AT91_CKGR_PLLBR, 0);
|
|
at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
|
|
|
|
/*
|
|
* MCK and CPU derive from one of those primary clocks.
|
|
* For now, assume this parentage won't change.
|
|
*/
|
|
mckr = at91_sys_read(AT91_PMC_MCKR);
|
|
mck.parent = clock_list[mckr & AT91_PMC_CSS];
|
|
mck.parent->users++;
|
|
freq = mck.parent->rate_hz;
|
|
freq /= (1 << ((mckr >> 2) & 3)); /* prescale */
|
|
mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */
|
|
|
|
printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
|
|
freq / 1000000, (unsigned) mck.rate_hz / 1000000,
|
|
(unsigned) main_clock / 1000000,
|
|
((unsigned) main_clock % 1000000) / 1000);
|
|
|
|
/* FIXME get rid of master_clock global */
|
|
at91_master_clock = mck.rate_hz;
|
|
|
|
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
|
|
/* establish PCK0..PCK3 parentage */
|
|
for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
|
|
struct clk *clk = clock_list[tmp], *parent;
|
|
u32 pckr;
|
|
|
|
if (!clk->programmable)
|
|
continue;
|
|
|
|
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
|
parent = clock_list[pckr & 3];
|
|
clk->parent = parent;
|
|
clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
|
|
}
|
|
#else
|
|
/* disable unused clocks */
|
|
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
|
|
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
|
|
|
|
/* FIXME several unused clocks may still be active... provide
|
|
* a CONFIG option to turn off all unused clocks at some point
|
|
* before driver init starts.
|
|
*/
|
|
|
|
return 0;
|
|
}
|