6eb9d32298
On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00 leads to _very poor_ performance as a PCI target since external burst won't be possible at all. Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> |
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| .. | ||
| efika.c | ||
| Kconfig | ||
| lite5200_pm.c | ||
| lite5200_sleep.S | ||
| lite5200.c | ||
| Makefile | ||
| mpc52xx_common.c | ||
| mpc52xx_gpio.c | ||
| mpc52xx_pci.c | ||
| mpc52xx_pic.c | ||
| mpc52xx_pic.h | ||
| mpc52xx_pm.c | ||
| mpc52xx_sleep.S | ||
| mpc5200_simple.c | ||