forked from luck/tmp_suning_uos_patched
dmaengine: ti: k3-psil-j721e: Add entries for 2nd port of MCU SA2UL
The security accelerator within MCU domain supports two ports similarly to the SA2UL in MAIN domain. Add endpoint configuration for the two ingress and one egress threads of the second port. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20200803100724.19003-1-peter.ujfalusi@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -166,6 +166,8 @@ static struct psil_ep j721e_src_ep_map[] = {
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/* SA2UL */
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PSIL_SA2UL(0x7500, 0),
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PSIL_SA2UL(0x7501, 0),
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PSIL_SA2UL(0x7502, 0),
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PSIL_SA2UL(0x7503, 0),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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@ -211,6 +213,7 @@ static struct psil_ep j721e_dst_ep_map[] = {
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PSIL_ETHERNET(0xf007),
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/* SA2UL */
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PSIL_SA2UL(0xf500, 1),
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PSIL_SA2UL(0xf501, 1),
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};
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struct psil_ep_map j721e_ep_map = {
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