forked from luck/tmp_suning_uos_patched
db6f41063c
On arm64, cache maintenance faults appear as data aborts with the CM bit set in the ESR. The WnR bit, usually used to distinguish between faulting loads and stores, always reads as 1 and (slightly confusingly) the instructions are treated as reads by the architecture. This patch fixes our fault handling code to treat cache maintenance faults in the same way as loads. Signed-off-by: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> |
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| .. | ||
| cache.S | ||
| context.c | ||
| copypage.c | ||
| dma-mapping.c | ||
| extable.c | ||
| fault.c | ||
| flush.c | ||
| hugetlbpage.c | ||
| init.c | ||
| ioremap.c | ||
| Makefile | ||
| mm.h | ||
| mmap.c | ||
| mmu.c | ||
| pgd.c | ||
| proc-macros.S | ||
| proc.S | ||
| tlb.S | ||