kernel_optimize_test/arch/riscv
Sagar Shrikant Kadam a416b33e8b dts: phy: add GPIO number and active state used for phy reset
[ Upstream commit a0fa9d727043da2238432471e85de0bdb8a8df65 ]

The GEMGXL_RST line on HiFive Unleashed is pulled low and is
using GPIO number 12. Add these reset-gpio details to dt-node
using which the linux phylib can reset the phy.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-01-27 11:55:01 +01:00
..
boot dts: phy: add GPIO number and active state used for phy reset 2021-01-27 11:55:01 +01:00
configs RISC-V: Add EFI stub support. 2020-10-02 14:31:21 -07:00
include riscv: Fixup CONFIG_GENERIC_TIME_VSYSCALL 2021-01-19 18:27:20 +01:00
kernel riscv: cacheinfo: Fix using smp_processor_id() in preemptible 2021-01-27 11:55:00 +01:00
lib riscv: use memcpy based uaccess for nommu again 2020-10-04 10:27:07 -07:00
mm riscv: Fix KASAN memory mapping. 2021-01-19 18:27:20 +01:00
net treewide: Use fallthrough pseudo-keyword 2020-08-23 17:36:59 -05:00
Kbuild
Kconfig RISC-V Patches for the 5.10 Merge Window, Part 2 2020-10-24 10:57:57 -07:00
Kconfig.debug
Kconfig.socs RISC-V: Remove CLINT related code from timer and arch 2020-08-20 10:58:13 -07:00
Makefile Kbuild updates for v5.10 2020-10-22 13:13:57 -07:00