[RISCV] Fix missing addi in test to validate lower inline asm m with offset

2023-03-16 13:24:22 -03:00 · 2023-03-16 13:24:22 -03:00 · 185ea867eb
commit 185ea867eb
parent 013f6d23e6
1 changed files with 2 additions and 0 deletions
--- a/llvm/test/CodeGen/RISCV/inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
@ -93,6 +93,8 @@ define i32 @constraint_m_with_offset(ptr %a) nounwind {
 ;
 ; RV64I-LABEL: constraint_m_with_offset:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 4
+; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret